Self-heating-based analysis of gate structures on junctionless nanowire transistors

机译：基于自加热的无结纳米线晶体管上栅极结构的分析

获取原文

获取原文并翻译 | 示例

页面导航

摘要
著录项
相似文献
相关主题

摘要

In this paper, an analysis on the thermal profile of Junctionless Nanowire Transistors is made, where self-heating effects are evaluated in devices with a large 4-contact gate, comparing the results with a minimized gate structure device. Tests are performed for different fin widths and fin heights. The analysis is based on three-dimensional simulations. Results showed that the gate structure is impactful to the thermal behavior of narrow small transistors, but not wide and tall ones.

机译：在本文中，对无结纳米线晶体管的热特性进行了分析，其中在具有大4触点栅极的器件中评估了自发热效应，并将结果与最小化的栅极结构器件进行了比较。针对不同的鳍片宽度和鳍片高度进行测试。该分析基于三维模拟。结果表明，栅极结构对窄小晶体管的热性能有影响，但对宽高晶体管却没有影响。

著录项

来源
《2017 32nd Symposium on Microelectronics Technology and Devices》|2017年|1-4|共4页
会议地点 Fortaleza(BR)
作者
F. E. Bergamaschi; M. A. Pavanello; G. Mariniello;
展开▼
作者单位

Electrical Engineering Department, Centro Universitário FEI, São Bernardo do Campo, Brazil;

Electrical Engineering Department, Centro Universitário FEI, São Bernardo do Campo, Brazil;

Electrical Engineering Department, FMU, São Paulo, Brazil;

展开▼
会议组织
原文格式 PDF
正文语种 eng
中图分类
关键词
Logic gates; Transistors; Temperature measurement; Heating systems; Thermal resistance; Metals;

机译：逻辑门;晶体管;温度测量;加热系统;热阻;金属;;

相似文献

外文文献
中文文献
专利

1. Mixed-mode simulation and analysis of 3D double gate junctionless nanowire transistor for CMOS circuit applications [J] . Achinta Baidya, Trupti Ranjan Lenka, Srimanta Baishya Superlattices and microstructures . 2016,第deca期

机译：用于CMOS电路的3D双栅极无结纳米线晶体管的混合模式仿真和分析
2. Localized Charge-Dependent Threshold Voltage Analysis of Gate-Material-Engineered Junctionless Nanowire Transistor [J] . Pratap Yogesh, Haldar Subhasis, Gupta Radhey Shyam, Electron Devices, IEEE Transactions on . 2015,第8期

机译：栅极材料工程化的无结纳米线晶体管的局部电荷相关阈值电压分析
3. Characteristic of p-Type Junctionless Gate-All-Around Nanowire Transistor and Sensitivity Analysis [J] . Han M.-H., Chang C.-Y., Jhan Y.-R., Electron Device Letters, IEEE . 2013,第2期

机译：p型无结全栅纳米线晶体管的特性及灵敏度分析
4. Self-Heating-based Analysis of Gate Structures on Junctionless Nanowire Transistors [C] . F. E. Bergamaschi, M. A. Pavanello, G. Mariniello Symposium on Microelectronics Technology and Devices . 2017

机译：无连接纳米线晶体管栅极结构的基于自热的分析
5. Nanowire-based devices for electronic and optical applications: Solution-gated silicon nanowire field effect transistors and one-dimensional gold nanoparticle arrays [D] . Hu, Wenchong 2010

机译：用于电子和光学应用的基于纳米线的设备：溶液门控硅纳米线场效应晶体管和一维金纳米粒子阵列
6. Characterizing the electrical properties of raised S/D junctionless thin-film transistors with a dual-gate structure [O] . Ya-Chi Cheng, Hung-Bin Chen, Jun-Ji Su, 2014

机译：表征具有双栅结构的凸起S / D无结薄膜晶体管的电性能
7. Electrical transfer, carrier concentration and surface charge analysis of a single-gated cylindrical channel junctionless p-type nanowire field-effect transistor for sensor applications [O] . Umapathi Krishnamoorthy, Sathish Kumar Shanmugam 2021

机译：用于传感器应用的单门控圆柱通道连接P型纳米线效应晶体管的电气传递，载流子浓度和表面电荷分析

Self-heating-based analysis of gate structures on junctionless nanowire transistors

摘要

著录项

相似文献

相关主题

期刊订阅