• 主题
高级搜索  >
历史搜索 清空历史
首页> 外文会议>26th International Symposium for Testing and Failure Analysis, Nov 12-16, 2000, Bellevue, Washington >Evaluation of On-Chip ESD Supply Clamp Robustness by In-situ Floating Power Bus Monitoring
【24h】

Evaluation of On-Chip ESD Supply Clamp Robustness by In-situ Floating Power Bus Monitoring

机译：通过现场浮动电源总线监控评估片上ESD电源夹的鲁棒性

获取原文
获取原文并翻译 | 示例
页面导航
  • 摘要
  • 著录项
  • 相似文献
  • 相关主题

摘要

Continuous improvements over time to a CMOS Flash Memory technology resulted in significant improvement in Human Body Model (HBM) ESD immunity for "I/O's" to Vcc power supply and Vss ground pins. Remaining low level failure modes in the die core included elevated standby current that in some cases could not be localized even with extensive chip de-processing. In addition an apparent functional failure upon post stress ATE test was isolated for certain part revisions. Routine separation of Vss/Vcc supply pin combinations from "all other pins" during HBM ESD test allowed identification of the several failures occurring in the die core. Failure analysis and corrective action is described. Additional diagnostic testing using separate polarity HBM pulses aided in tracing the conduction path causing the apparent functional failure and prompted investigation of HBM tester dynamic properties. It was determined that the magnitude of the "second" HBM pulse in certain testers was sufficient to cause a false power-up condition which results in apparent functional failure upon subsequent ATE test. In-situ monitoring of the Floating Power Bus response (in this case Vss) during application of HBM stress to the Input-pad to Vcc-pin combination revealed a transient caused by the "second" pulse that allowed such apparent failures to be invalidated. Further more, monitoring the in-situ floating Vss bus response to the HBM allowed conclusions to be drawn as to the utility of different power bus and Vss/Vcc supply clamp layouts, thereby allowing improvements to die layout to be implemented.
机译：随着时间的推移，对CMOS闪存技术的不断改进导致针对Vcc电源和Vss接地引脚的“ I / O”的人体模型（HBM）ESD抗扰性得到了显着改善。管芯中剩余的低水平故障模式包括升高的待机电流，在某些情况下，即使进行大量的芯片处理，也无法将其定位。此外，对于某些零件修订版，隔离了应力后ATE测试中的明显功能故障。在HBM ESD测试期间，通过将Vss / Vcc电源引脚组合与“所有其他引脚”进行常规分离，可以识别出芯片芯中发生的几种故障。描述了故障分析和纠正措施。使用单独的极性HBM脉冲进行的其他诊断测试有助于跟踪导致明显功能故障的导电路径，并有助于研究HBM测试仪的动态特性。已确定在某些测试仪中“第二” HBM脉冲的大小足以引起错误的加电条件，从而在随后的ATE测试中导致明显的功能故障。在将HBM应力施加到输入板至Vcc引脚的组合过程中，对浮动电源总线响应（在本例中为Vss）进行现场监控，发现由“第二”脉冲引起的瞬变使这种明显的故障失效。此外，监视现场浮动Vss总线对HBM的响应，可以得出关于不同电源总线和Vss / Vcc电源钳位布局的效用的结论，从而可以改进裸片布局。

著录项

相似文献

  • 外文文献
  • 中文文献
  • 专利
获取原文

客服邮箱：kefu@zhangqiaokeyan.com

京公网安备：11010802029741号 ICP备案号：京ICP备15016152号-6 六维联合信息科技 (北京) 有限公司©版权所有

  • 客服微信

  • 服务号