A 0.8/0.9-V 5.4-GHz phase-locked loop with inductance coupled VCO in 0.18-??m CMOS

机译：0.8 / 0.9-V 5.4-GHz锁相环，电感耦合VCO，0.18-ΩmCMOS

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Implemented in a standard 0.18-??m CMOS process, a 0.8/0.9-V 5.4-GHz low-power phase-locked loop (PLL) is presented. In the prescaler, the first-stage divide-by-2 prescaler is structed with LC-type VCO by inductance coupled to perform frequency division. The next-stage divide-by-2 divider uses the conventional D-type filpflop with optimizing the threshold voltage to lower the operating voltage. As the building blocks are optimized for low-voltage and low-power operations, the fabricated 5.4-GHz PLL consumes a dc power of 4.8 mW from a 0.8/0.9-V and phase noise of ???109.6 dBc/Hz at 1-MHz offset.

机译：采用标准的0.18-μmCMOS工艺实现，提出了0.8 / 0.9-V 5.4-GHz低功率锁相环（PLL）。在预分频器中，第一级二分频预分频器由LC型VCO通过耦合电感来进行分频构成。下一级2分频器使用常规D型滤波器，优化了阈值电压以降低工作电压。由于针对低电压和低功率操作对构建模块进行了优化，因此，制造出来的5.4 GHz PLL在0.8 / 0.9-V时消耗4.8 mW的直流功率，在1-时的相位噪声为109.6 dBc / Hz。 MHz偏移。

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来源
《4th International Symposium on Bioelectronics and Bioinformatics》|2015年|75-78|共4页
会议地点 Beijing(CN)
作者
Weng Jun-Hong; Lin Yen-Chen; Cheng Shen; Chiu Chih-Kai;
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作者单位

Department of Electrical Engineering, Tunghai University, Taichung, Taiwan;

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原文格式 PDF
正文语种 eng
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关键词
low voltage; phase-locked loop (PLL); voltage-controlled oscillator (VCO);

机译：低压;锁相环（PLL）;压控振荡器（VCO）;

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专利

1. 11.6-GHz 0.18-μm CMOS锁相环电路 [J] . 王骏峰, 冯军, 李义慧, 东南大学学报（英文版） . 2007,第001期
2. Linear CMOS -VCO Based on Triple-Coupled Inductors and Its Application to 40-GHz Phase-Locked Loop [J] . Zhe Chen, Ming Wang, Ji-Xin Chen, IEEE Transactions on Microwave Theory and Techniques . 2017,第8期

机译：基于三耦合电感的线性CMOS -VCO及其在40 GHz锁相环中的应用
3. Record Q symmetrical inductors for 10-GHz LC-VCOs in 0.18-/spl mu/m gate-length CMOS [J] . Tiemeijer L.F., Havens R.J., Pavlovic N., IEEE Electron Device Letters . 2002,第12期

机译：在0.18- / splμ/ m栅极长度CMOS中为10-GHz LC-VCO记录Q对称电感器
4. A Low Power 622 MHz CMOS Phase-Locked Loop with Source Coupled VCO and Dynamic PFD [J] . Hiroyasu YOSHIZAWA, Kenji TANIGUCHI, Hiroyuki SHIRAHAMA, IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences . 1997,第6期

机译：具有电源耦合VCO和动态PFD的低功耗622 MHz CMOS锁相环
5. A 0.8/0.9-V 5.4-GHz phase-locked loop with inductance coupled VCO in 0.18-??m CMOS [C] . Weng Jun-Hong, Lin Yen-Chen, Cheng Shen, International Symposium on Bioelectronics and Bioinformatics . 2015

机译：0.8 / 0.9-V 5.4-GHz锁相环，电感耦合VCO 0.18 - ?? M CMOS
6. CMOS VCO and LNA implemented by air-suspended on-chip RF MEMS inductors. [D] . Shenoy, Varun K. 2007

机译：CMOS VCO和LNA由空气悬浮的片上RF MEMS电感器实现。
7. CMOS 120 GHz Phase-Locked Loops Based on Two Different VCO Topologies [O] . Junghwan Yoo, Jae-Sung Rieh 2017

机译：基于两个不同的VCO拓扑拓扑拓扑的CMOS 120 GHz锁相环

A 0.8/0.9-V 5.4-GHz phase-locked loop with inductance coupled VCO in 0.18-??m CMOS

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