Edge Defined Lithography for Nano-scale Ⅲ-N Field Effect Transistors

机译：纳米级Ⅲ-N场效应晶体管的边缘定义光刻

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摘要

In this work we demonstrate a method by which sub-100 nm features can be fabricated using only conventional semiconductor processing and optical lithography techniques. This methodology uses no e-beam in the process but has the potential to create lithographically located features at dimensions approaching 5 nm. The successful process becomes an exercise in thin film process control, rather than lithography process control. To achieve this, we present several of the key issues surrounding the optimization process required to implement this technology and to exploit fully its potential.

机译：在这项工作中，我们演示了仅使用常规半导体处理和光刻技术即可制造100 nm以下特征的方法。该方法在该过程中不使用电子束，但有可能在尺寸接近5 nm的位置上创建光刻定位的特征。成功的过程成为薄膜过程控制而非光刻过程控制中的一项工作。为了实现这一目标，我们提出了围绕实现该技术并充分利用其潜力所需的优化过程的几个关键问题。

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来源
《Annual International Conference on Compound Semiconductor MANufacturing TECHnology(CS MANTECH); 20050411-14; New Orleans,LA(US)》|2005年|P.327-330|共4页
会议地点 New OrleansLA(US)
作者
J.P. Long; C. Zeng; Y.Jin; D.W. Barlage; M.A.L. Johnson;
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作者单位

North Carolina State University, Raleigh NC;

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会议组织
原文格式 PDF
正文语种 eng
中图分类半导体技术;
关键词
spacer gate; edge defined lithography; MOSFET; GaN;

机译：间隔栅;边沿光刻; MOSFET; GaN;

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专利

1. Stability Of Hsq Nanolines Defined By E-beam Lithography For Si Nanowire Field Effect Transistors [J] . Suresh Regonda, Mukti Aryal, Wenchuang (Walter) Hu Journal of Vacuum Science & Technology. B, Microelectronics and Nanometer Structures . 2008,第6期

机译：电子束光刻技术定义的Hsq纳米线对Si纳米线场效应晶体管的稳定性
2. Effects of Line-Edge Roughness on Extreme Ultraviolet Lithography CDs and Fin-Field-Effect-Transistor Performance for Below 10-nm Patterns [J] . Kim Sang-Kon Journal of nanoscience and nanotechnology . 2017,第11期

机译：线边缘粗糙度对极端紫外线光刻CDS和Fin场效应晶体管性能的影响，低于10nm图案
3. Structural Studies on Superconducting Flux Flow Transistors with Nano-Scale Channel Fabricated by Electron Beam Lithography [J] . Seok-Cheol Ko Journal of nanoscience and nanotechnology . 2013,第10期

机译：电子束光刻技术制备的纳米级通道超导通量流晶体管的结构研究
4. Edge Defined Lithography for Nano-scale III-N Field Effect Transistors [C] . J. P. Long, C. Zeng, Y. Jin, Annual International Conference on Compound Semiconductor MANufacturing TECHnology . 2005

机译：用于纳米级III-N场效应晶体管的边缘定义光刻
5. Reduction of line edge roughness (ler) in interference-like large field lithography. [D] . Baylav, Burak. 2014

机译：减少类似干涉的大场光刻中的线边缘粗糙度（ler）。
6. Improved sensing characteristics of dual-gate transistor sensor using silicon nanowire arrays defined by nanoimprint lithography [O] . Cheol-Min Lim, In-Kyu Lee, Ki Joong Lee, 2017

机译：使用由纳米压印光刻技术定义的硅纳米线阵列改善双栅晶体管传感器的感测特性
7. Tcad-based statistical analysis and modeling of gate line-edge roughness effect on nano-scale mos transistor performance and scaling [O] . Seong-dong Kim, Hideyuki Wada, Jason C. S. Woo, 2004

机译：基于Tcad的栅极线边缘粗糙度统计分析和建模对纳米级mos晶体管性能和缩放的影响
8. Studies by Near Edge X-ray Absorption Spectroscopies of Bonding Dynamics at the Graphene/Guanine Interface - A Proposal for High Mobility, Organic Graphene Field Effect Transistors. [R] . Campo, E. 2015

机译：石墨烯/鸟嘌呤界面粘接动力学近边缘X射线吸收光谱研究 - 高迁移率，有机石墨烯场效应晶体管的建议。

Edge Defined Lithography for Nano-scale Ⅲ-N Field Effect Transistors

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