• 主题
高级搜索  >
历史搜索 清空历史
首页> 外文会议>Conference on Design for Manufacturability through Design-Process Integration; 20080128-29; San Jose,CA(US) >Manufacturing for Design: A Novel Interconnect Optimization Method
【24h】

Manufacturing for Design: A Novel Interconnect Optimization Method

机译：设计制造：一种新型的互连优化方法

获取原文
获取原文并翻译 | 示例
页面导航
  • 摘要
  • 著录项
  • 相似文献
  • 相关主题

摘要

Disconnection between design and manufacturing has become a prevalent issue in modern VLSI processes. As manufacturability becomes a major concern, uncertainties from process variation and complicated rules have increased the design cost exponentially. Numerous design methodologies for manufacturability have been proposed to improve the yield. In deep submicron designs, optical proximity correction (OPC) and fill insertion have become indispensable for chip fabrication. In this paper, we propose a novel method to use these manufacturing techniques to optimize the design. We can effectively implement non-uniform wire sizing and achieve substantial performance and power improvement with very low costs on both design and manufacturing sides. The proposed method can reduce up to 42% power consumption without any delay penalty. It brings minor changes to the current design flow and no extra cost for fabrication.
机译：设计与制造之间的脱节已成为现代VLSI工艺中的普遍问题。随着可制造性成为主要问题，工艺变化和复杂规则带来的不确定性成倍增加了设计成本。已经提出了许多可制造性的设计方法，以提高产量。在深亚微米设计中，光学接近度校正（OPC）和填充物插入对于芯片制造已变得不可或缺。在本文中，我们提出了一种使用这些制造技术来优化设计的新颖方法。我们可以有效地实现尺寸不均匀的布线，并以非常低的成本在设计和制造方面实现实质性的性能和功率提升。所提出的方法可以减少多达42％的功耗，而不会造成任何延迟损失。它对当前的设计流程进行了微小的更改，并且没有额外的制造成本。

著录项

相似文献

  • 外文文献
  • 中文文献
  • 专利
获取原文

客服邮箱：kefu@zhangqiaokeyan.com

京公网安备：11010802029741号 ICP备案号：京ICP备15016152号-6 六维联合信息科技 (北京) 有限公司©版权所有

  • 客服微信

  • 服务号