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Taming the final frontier of optical lithography: Design for sub-resolution patterning

机译：驯服光学光刻的最终领域：亚分辨率图案设计

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摘要

The 20nm node, with a targeted wiring pitch of 64nm, is the first technology node to dip below the fundamental k_1=0.25 resolution limit of high-NA 193nm immersion lithography. Double-patterning has been applied in previous technology nodes to address specific image quality issues such as line-end shortening or poor process window on contacts and vias, but never before has double-patterning been used to form images below the frequency-doubled resolution-limit of optical lithography. This paper describes the design-technology co-optimization efforts exercised by the alliance program for Bulk CMOS technology development at IBM in pursuit of cost-effective double-patterning for the 20nm technology node. The two primary double-patterning contenders, pitch-splitting and sidewall-image-transfer, are reviewed and their unique layout decomposition requirements are contrasted. Double-patterning design enablement solutions and their particular applicability to each step in the design flow are described. The paper closes with a review of the cost-effectiveness of current double-patterning solutions, highlighting the important role of design-technology co-optimization in ensuring continued cost-effective semiconductor scaling.
机译：目标布线间距为64nm的20nm节点是第一个跌落到高NA 193nm浸没式光刻技术的基本k_1 = 0.25分辨率极限以下的技术节点。在先前的技术节点中已经采用了双重图案化技术来解决特定的图像质量问题，例如线端缩短或触点和过孔上的工艺窗口差，但是以前从未使用双重图案化技术来形成低于倍频分辨率的图像，光刻的极限。本文描述了联盟计划在IBM进行Bulk CMOS技术开发时所进行的设计技术共同优化工作，以寻求具有成本效益的20nm技术节点双图案。审查了两个主要的双图案竞争者，间距分裂和侧壁图像转移，并对比了其独特的布局分解要求。描述了双模式设计使能解决方案及其在设计流程中每个步骤的特殊适用性。本文在总结当前双图案解决方案的成本效益时结束，强调了设计技术协同优化在确保持续的成本效益半导体缩放方面的重要作用。

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