3D Interconnect: The Challenges Ahead

机译：3D互连：未来的挑战

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3D package solutions now account for a significant portion (~20%) of all die arearnprocessed today. Most all of this is still assembled in standard package configurationsrn(FBGA, SO, MicroSD, etc) using wirebond interconnect. This paper will look at thernmany current technologies that have been adopted to enable 3D, and understand what thernnext steps will be to enable true die to die interconnection in a cost effective manner.rnRecent examples of various technologies from Fan-out WL-CSP, TSV for image sensorsrnand MEMS, and other 3D concepts will be shown to highlight advantages andrndisadvantages of these emerging technologies. Prismark's roadmap for 3D adoption willrnbe compared to previous new technology roadmaps to demonstrate the history of olderrntechnologies' ability to hang on to market share.

机译：现在，3D封装解决方案占当今所有裸片加工的很大一部分（约20％）。所有这些大多数仍使用引线键合互连组装在标准封装配置中（FBGA，SO，MicroSD等）。本文将探讨为实现3D而采用的许多最新技术，并了解下一步将采取哪些步骤以成本有效的方式实现真正的芯片到芯片互连。扇出WL-CSP，TSV的各种技术的最新示例用于图像传感器和MEMS的技术，以及其他3D概念将被展示出来，以突出这些新兴技术的优缺点。 Prismark的3D采用路线图将与以前的新技术路线图进行比较，以展示较早的技术保持市场份额的能力的历史。

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来源
《Device packaging 2010》|2010年|p.1|共1页
会议地点 Scottsdale/Fountain Hills AZ(US)
作者
Brandon Prior;
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作者单位

Prismark Partnersrn130 Main StreetrnCold Spring Habor, NY 11724rnP: 631-367-9187rnE: bprior@prismark.com;

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原文格式 PDF
正文语种 eng
中图分类制造工艺;
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3D Interconnect: The Challenges Ahead

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