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AlGaN/GaN MIS-HEMT Gate Structure Improvement Using Al_2O_3 Deposited by PEALD and BCl_3 Gate Recess Etching

机译:利用PEALD沉积Al_2O_3和BCl_3栅凹槽刻蚀改善AlGaN / GaN MIS-HEMT栅结构。

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摘要

The enhancement of electric properties of MIS structures on an AlGaN/GaN heterostructure using Al_2O_3 a gate dielectric are investigated using C(V) and I_d(V_g) measurements. The Al_2O_3 layer was deposited using two types of atomic layer deposition (ALD) techniques: thermal ALD and plasma enhanced ALD. Using PEALD over thermal ALD led to an increase of the threshold voltage V_(th) of 4V, and the suppression of non-uniform C(V) behavior by reducing traps at the Al_2O_3/AlGaN interface. Gate leakage current was also reduced by 6 decades and an I_(on)/I_(off) ratio of 10~9 was achieved, with a subthreshold slope of 81mV/decades. Further improvements were achieved by gate recess etching before the high-k deposition through BCl_3 reactive ion etching (RIE). We were able to further increase V_(th) by 4V while reducing gate leakage current, achieving a 10~(10) I_(on)/I_(off) ratio, without degrading the subthreshold slope and the abruptness of the transition.
机译:使用C(V)和I_d(V_g)测量研究了使用Al_2O_3 a栅极电介质在MISGaN结构上的GaN结构的电性能增强。使用两种类型的原子层沉积(ALD)技术沉积Al_2O_3层:热ALD和等离子体增强ALD。在热ALD上使用PEALD导致阈值电压V_(th)增加4V,并通过减少Al_2O_3 / AlGaN界面处的陷阱来抑制不均匀的C(V)行为。栅极漏电流也减少了6十年,I_(on)/ I_(off)比率​​达到10〜9,亚阈值斜率达到81mV / decade。在通过BCl_3反应离子刻蚀(RIE)进行高k沉积之前,通过栅极凹槽刻蚀实现了进一步的改进。我们能够将V_(th)进一步提高4V,同时降低栅极泄漏电流,达到10〜(10)的I_(on)/ I_(off)比率​​,而不会降低亚阈值斜率和跃迁的突变性。

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  • 会议地点 San Francisco CA(US)
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    CEA-Leti, MINATEC Campus, 17 Rue des martyrs, 38054 Grenoble Cedex 9, France;

    CEA-Leti, MINATEC Campus, 17 Rue des martyrs, 38054 Grenoble Cedex 9, France;

    CEA-Leti, MINATEC Campus, 17 Rue des martyrs, 38054 Grenoble Cedex 9, France;

    CEA-Leti, MINATEC Campus, 17 Rue des martyrs, 38054 Grenoble Cedex 9, France;

    CEA-Leti, MINATEC Campus, 17 Rue des martyrs, 38054 Grenoble Cedex 9, France;

    LAAS-CNRS, 7 Avenue du Colonel Roche, 31400 Toulouse, France;

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