Interconnect materials challenges for sub 20 nm technology nodes: Ultra low-k dielectrics

机译：低于20 nm技术节点的互连材料挑战：超低k电介质

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This presentation is an overview of ultra low dielectric constant (low-k) materials that have been developed for sub 20 nm technology nodes. These dielectrics include highly porous organosilicate glasses (OSG: both PECVD and spin-on) and new classes of materials like metal organic frameworks (MOF) and covalent organic frameworks (COF). In addition to the extended overview of the materials properties, new technological approaches helping to reduce plasma induced degradation (damage) and allowing the pore sealing are also discussed. For the plasma damage reduction, pore stuffing technologies are considered as promising. For the sealing of ultra low-k materials that have pore size larger than 3–5 nm, special PMO (periodic mesoporous oxide) have been developed and discussed.

机译：本演讲概述了针对20 nm以下技术节点开发的超低介电常数（low-k）材料。这些电介质包括高度多孔的有机硅酸盐玻璃（OSG：PECVD和旋涂）以及新型材料，例如金属有机骨架（MOF）和共价有机骨架（COF）。除了扩展了材料性能概述之外，还讨论了有助于减少等离子体引起的降解（损坏）并允许孔密封的新技术方法。为了减少等离子体损伤，毛孔填充技术被认为是有前途的。为了密封孔径大于3-5 nm的超低k材料，已经开发并讨论了特殊的PMO（周期性中孔氧化物）。

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来源
《IEEE International Conference on Solid-State and Integrated Circuit Technology;ICSICT-2012》|2012年|p.1-3|共3页
会议地点 Xi'an(CN);Xi'an(CN)
作者
Baklanov, Mikhail R.;
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imec Leuven 3001 Belgium;

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interconnect technology; low-k materials; microelectronics; porosity;

机译：互连技术；低k材料微电子学孔隙率;

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专利

1. Effective Cu surface pre-treatment for high-reliable 22 nm-node Cu dual damascene interconnects with high plasma resistant ultra low-k dielectric (k = 2.2) [J] . F. Ito, H. Shobha, M. Tagami, Microelectronic Engineering . 2012,第Apra期

机译：有效的铜表面预处理，用于具有高耐等离子体性的超低介电常数（k = 2.2）的高可靠性22 nm节点铜双镶嵌互连
2. Sidewall restoration of porous ultra low-k dielectrics for sub-45 nm technology nodes [J] . H. Chaabouni, L.L. Chapelon, M. Aimadeddine, Microelectronic Engineering . 2007,第11期

机译：低于45 nm技术节点的多孔超低k电介质的侧壁修复
3. Evaluation of Post Etch Residue Cleaning Solutions for the Removal of Tin Hardmask after Dry Etch of Low-K Dielectric Materials on 45 nm Pitch Interconnects [J] . Makonnen Payne, Steve Lippy, Ruben Lieten, Diffusion and Defect Data. Solid State Data, Part B. Solid State Phenomena . 2016,第Null期

机译：在45 nm间距互连线上干蚀刻低K介电材料后去除锡硬掩模的蚀刻后残留清洗液的评估
4. Interconnect materials challenges for sub 20 nm technology nodes: Ultra low-k dielectrics [C] . Baklanov Mikhail R. International Conference on Solid-State and Integrated Circuit Technology . 2012

机译：互连材料挑战SUB 20 NM技术节点：超低k电介质
5. Mechanical reliability of porous low-k dielectrics for advanced interconnect: Study of the instability mechanisms in porous low-k dielectrics and their mediation through inert plasma induced re-polymerization of the backbone structure. [D] . Sa, Yoonki. 2015

机译：用于高级互连的多孔低k电介质的机械可靠性：多孔低k电介质的不稳定性机理及其通过惰性等离子体引发的骨架结构再聚合的介导研究。
6. Material design of plasma-enhanced chemical vapour deposition SiCH films for low-k cap layers in the further scaling of ultra-large-scale integrated devices-Cu interconnects [O] . Hideharu Shimizu, Shuji Nagano, Akira Uedono, 2013

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7. Dielectric/metal diffusion barrier in Cu/porous ultra low-k interconnect technology [O] . Zhe Chen -1

机译：Cu /多孔超低k互连技术中的介质/金属扩散屏障

Interconnect materials challenges for sub 20 nm technology nodes: Ultra low-k dielectrics

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