TUNNEL DIODE/TRANSISTOR DIFFERENTIAL COMPARATOR

机译：隧道二极管/晶体管差分比较器

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A new tunnel diode/transistor circuit topology is reported, which both increases speed and reduces power in differential comparators. This circuit topology is of special interest for use in direct digital synthesis applications. The circuit topology can be extended to provide performance improvements in high speed logic and signal processing applications. The circuits are designed based on InP/GaAsSb double heterojunction bipolar transistors and AlAs/InGaAs/AlAs resonant tunneling diodes. A self-aligned and scalable fabrication approach using nitride sidewalls and chemical mechanical polishing is outlined.

机译：报告了一种新的隧道二极管/晶体管电路拓扑，它既提高了速度，又降低了差分比较器中的功率。对于直接数字合成应用中使用的电路拓扑特别感兴趣。可以扩展电路拓扑，以提高高速逻辑和信号处理应用程序的性能。该电路是基于InP / GaAsSb双异质结双极晶体管和AlAs / InGaAs / AlAs共振隧穿二极管设计的。概述了一种使用氮化物侧壁和化学机械抛光的自对准且可扩展的制造方法。

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来源
《IEEE Lester Eastman Conference on High Performance Devices; 20040804-06; Rensselaer Polytechnic Institute》|2004年|P.16-21|共6页
会议地点 Rensselaer Polytechnic Institute
作者
QINGMIN LIU; SURAJIT SUTAR; ALAN SEABAUGH;
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作者单位

Department of Electrical Engineering, University of Notre Dame Notre Dame, IN 46556, USA;

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原文格式 PDF
正文语种 eng
中图分类半导体技术;
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专利

1. TUNNEL DIODE/TRANSISTOR DIFFERENTIAL COMPARATOR [J] . Qingmin Liu, Surajit Sutar, Alan Seabaugh International Journal of High Speed Electronics and Systems: Devices, Integrated Circuits and Systems, Optical and Quantum Electronics . 2004,第3期

机译：隧道二极管/晶体管差分比较器
2. Design approach using tunnel diodes for lowering power in differential comparators [J] . Qingmin Liu, Seabaugh A. IEEE transactions on circuits and systems. II, Express briefs . 2005,第9期

机译：使用隧道二极管降低差分比较器功耗的设计方法
3. Design Approach Using Tunnel Diodes for Lowering Power in Differential Comparators [J] . Qingmin Liu, Alan Seabaugh IEEE Transactions on Circuits and Systems. II, Express Briefs . 2005,第9期

机译：使用隧道二极管降低差分比较器功耗的设计方法
4. TUNNEL DIODE/TRANSISTOR DIFFERENTIAL COMPARATOR [C] . QINGMIN LIU, SURAJIT SUTAR, ALAN SEABAUGH, IEEE Lester Eastman Conference on High Performance Devices . 2005

机译：隧道二极管/晶体管差分比较器
5. A Quantum Simulation Study of III-V Esaki Diodes and 2D Tunneling Field-effect Transistors [D] . Cadareanu, Patsy. 2018

机译：III-V Esaki二极管和2D隧穿场效应晶体管的量子模拟研究
6. Resonant tunnelling and negative differential conductance in graphene transistors [O] . L. Britnell, R. V. Gorbachev, A. K. Geim, -1

机译：石墨烯晶体管中的共振隧穿和负差分电导
7. Theory of asymmetric and negative differential magnon tunneling under temperature bias: Towards a spin Seebeck diode and transistor [O] . Ren, Jie, Zhu, Jian-Xin 2013

机译：非对称和负微分磁振子隧道的理论温度偏置：朝向旋转塞贝克二极管和晶体管

TUNNEL DIODE/TRANSISTOR DIFFERENTIAL COMPARATOR

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