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首页> 外文会议>IMAPS 40th international symposium on microelectronics >Wafer-Level Integration Technology with Heterogeneous Chip Redistribution and Inter-Chip Layer Process
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Wafer-Level Integration Technology with Heterogeneous Chip Redistribution and Inter-Chip Layer Process

机译：具有异构芯片再分配和芯片间层工艺的晶圆级集成技术

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摘要

The authors have proposed a pseudo-SOC (System on Chip) technology, a novel integration technology forming inter-chip layer with semiconductor process techniques on a chip-redistributed wafer with heterogeneous device chips encapsulated with inter-chip resin. This is a novel integration technology realizing a thinned package structure with fine inter-chip layer, unattainable with the previous SIP (System in Package) technology and integration of heterogeneous devices unattainable with the previous SOC technology. A stress analysis for realizing a pseudo-SOC structure for minimizing the strain in the integrated chips was carried out. A pseudo SOC with narrow gap and thinned structure was fabricated. An RF-receiver was also demonstrated using pseudo-SOC technology and the integration density was confirmed to be 16 times higher than the conventional SIP technology.
机译：作者提出了伪SOC（片上系统）技术，这是一种新颖的集成技术，该技术利用半导体工艺技术在芯片分布的晶片上形成了芯片间层，并且异质器件芯片被芯片间树脂封装。这是一种新颖的集成技术，实现了具有精细芯片间层的薄型封装结构，这是以前的SIP（系统级封装）技术无法实现的，并且异构器件的集成是以前的SOC技术无法实现的。进行应力分析以实现使最小化集成芯片中的应变的伪SOC结构。制作了间隙窄，结构薄的伪SOC。还使用伪SOC技术演示了RF接收器，并证实集成密度比传统SIP技术高16倍。

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