A CMOS low-power lock-in amplifier

机译：CMOS低功耗锁相放大器

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A novel analog lock-in amplifier designed in a 0.18µm CMOS process with a single supply voltage of 1:8V is presented in this paper. The proposed architecture recovers the signal of interest from noisy environments with errors below 5% for noise signals of the same amplitude as the signal of interest. The lock-in amplifier is suitable for portable applications thanks to its reduced power consumption and single-supply voltage operation. Post-layout simulation results show a variable DC gain ranging from 20 to 40dB, input-referred noise of 28.1µVrms, power consumption of 350.9 µW and area of (205×58) µm².

机译：本文介绍了一种新颖的模拟锁定放大器，它采用0.18µm CMOS工艺设计，单电源电压为1：8V。所提出的架构从噪声环境中恢复感兴趣的信号，对于与感兴趣的信号具有相同幅度的噪声信号，其误差低于5％。锁相放大器具有较低的功耗和单电源供电，因此适合便携式应用。布局后的仿真结果表明，可变直流增益在20至40dB之间，输入参考噪声为28.1µVrms，功耗为350.9 µW，面积为（205×58）µm ^{2 。}

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来源
《Instrumentation and Measurement Technology Conference (I2MTC), 2012 IEEE International》|2012年|p.1804- 1807|共4页
会议地点 Graz(AT)
作者
Maya-Hernaandez P.M.; Sanz-Pascual M.T.; Calvo B.; Antolin D.;
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作者单位

Electronic Department, Instituto Nacional de Astrofísica, Óptica y Electrónica, Tonantzintla, Puebla, México;

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原文格式 PDF
正文语种 eng
中图分类计量学;
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A CMOS low-power lock-in amplifier

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