A Linear Systolic Array for Multiplication in GF(2~m) for High Speed Cryptographic Processors

机译：用于高速加密处理器的GF（2〜m）中乘法的线性脉动阵列

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We present new designs of low complexity and low latency systolic arrays for multiplication in GF(2~m) when there is an irreducible all one polynomial (AOP) of degree m. Our proposed bit parallel array has a reduced latency and hardware complexity compared with previously proposed designs. For a cryptographic purpose, we derive a linear systolic array using our algorithm and show that our design has a latency m/2 + 1 and a throughput rate l/(m/2 + 1). Compared with other linear systolic arrays, we find that our design has at least 50 percent reduced hardware complexity and latency, and has twice higher throughput rate. Therefore our multiplier provides a fast and a hardware efficient architecture for multiplication of two elements in GF(2~m) for large m.

机译：我们提出了一种新的低复杂度和低等待时间的脉动阵列的新设计，用于在GF（2〜m）上具有不可约的m次多项式（AOP）的情况下。与先前提出的设计相比，我们提出的位并行阵列具有降低的延迟和硬件复杂性。为了达到加密目的，我们使用我们的算法得出线性脉动阵列，并表明我们的设计的延迟为m / 2 + 1，吞吐率为l /（m / 2 + 1）。与其他线性脉动收缩阵列相比，我们发现我们的设计将硬件复杂性和延迟降低了至少50％，并且吞吐速率提高了两倍。因此，我们的乘法器为大m的GF（2〜m）中的两个元素的乘法提供了一种快速且硬件有效的体系结构。

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来源
《International Conference on Computational Science and Its Applications(ICCSA 2004) pt.4; 20040514-20040517; Assisi; IT》|2004年|P.106-116|共11页
会议地点 Assisi(IT);Assisi(IT)
作者
Soonhak Kwon; Chang Hoon Kim; Chun Pyo Hong;
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作者单位

Inst. of Basic Science and Dept. of Mathematics, Sungkyunkwan University, Suwon 440-746, Korea;

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会议组织
原文格式 PDF
正文语种 eng
中图分类理论、方法;
关键词
finite field multiplier; systolic array; all one polynomial; riemann hypothesis; artin's conjecture for primitive roots;

机译：有限域乘数；脉动阵列；所有一个多项式； riemann假设；原始根的阿廷猜想;

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机译：基于系统线性阵列结构的RSA公钥密码协同处理器的FPGA实现
2. FPGA IMPLEMENTATION OF RSA PUBLIC-KEY CRYPTOGRAPHIC COPROCESSOR BASED ON SYSTOLIC LINEAR ARRAY ARCHITECTURE [J] . Wen Nuan, Dai Zibin, Zhang Yongfu 电子科学学刊（英文版） . 2006,第005期

机译：基于系统线性阵列结构的RSA公钥密码协同处理器的FPGA实现
3. High speed modular multiplication for elliptic curve cryptography on GF(p) [J] . Zheng Chuyu, Mastaka Ohta, Kiyomichi Araki 電子情報通信学会技術研究報告. 情報セキュリティ. Information Security . 2003,第61期

机译：GF（p）上椭圆曲线密码的高速模块化乘法
4. Compact Linear Systolic Arrays for Multiplication Using a Trinomial Basis in GF(2~m) for High Speed Cryptographic Processors [C] . Soonhak Kwon, Chang Hoon Kim, Chun Pyo Hong International Conference on Computational Scinece and Its Applications(ICCSA 2005) pt.1; 20050509-12; Singapore(SG) . 2005

机译：紧凑型线性脉动阵列，用于高速加密处理器的GF（2〜m）中的三项基乘运算
5. VHDL Implementation of PPR Systolic Array Architecture for Polynomial GF(2m) Multiplication. [D] . Nia, Ali. 2013

机译：用于多项式GF（2m）乘法的PPR脉动阵列结构的VHDL实现。
6. Parallel point-multiplication architecture using combined group operations for high-speed cryptographic applications [O] . Md Selim Hossain, Ehsan Saeedi, Yinan Kong -1

机译：使用组合组运算的并行点乘法架构用于高速密码应用
7. Design of a linear systolic array for computing modular multiplication and squaring in GF(2m) [O] . Lee Won-Ho, Lee Keon-Jik, Yoo Kee-Young 2001

机译：用于计算GF（2m）中的模块乘法和平方的线性脉动阵列的设计
8. High Speed Systolic Array Processor (HiSSAP) System Development Synopsis: LessonLearned [R] . Loughlin, J. P. 1991

机译：高速脉动阵列处理器（Hissap）系统开发概要：LessonLearned

A Linear Systolic Array for Multiplication in GF(2~m) for High Speed Cryptographic Processors

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