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首页> 外文会议>International VLSI multilevel interconnection conference;VMIC >Effects of Argon Plasma Preclean on non-Salicide Silicon Contact Resistance for non-Volatile Memory
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Effects of Argon Plasma Preclean on non-Salicide Silicon Contact Resistance for non-Volatile Memory

机译：氩等离子体预清洗对非易失性记忆的非硅化物硅接触电阻的影响

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摘要

As the contact size is shrunk, there exists limitation of wet preclean for contact metallization. The plasma preclean is intended to remove the native oxide at the contact bottom and thus reduce contact resistance. A series of experiments of contact plasma preclean were conducted on non-volatile memory contact. Plasma clean of dual-frequency method were employed to carry out this study. The experimental conditions were RF/bias powers and preclean thickness removal with respect to thermal oxide. The contact resistance was increased as DC bias and preclean thickness were increased. In addition, the wafers with plasma preclean greater than 200A were out of electrical specification for two plasma power conditions of 150W/300W and 300W/300W. The silicon loss was characterized with SEM. Serious silicon loss was observed on the wafer with preclean of high DC bias and high preclean thickness as compared with those without preclean. More silicon loss resulted in higher resistance of contact chain. Low DC bias power and optimized preclean thickness removal should be used to optimize the plasma preclean process for eliminating plasma damage.
机译：随着接触尺寸的缩小，存在用于接触金属化的湿法预清洁的局限性。等离子体预清洗旨在去除接触底部的自然氧化物，从而降低接触电阻。在非易失性存储器触点上进行了接触等离子体预清洗的一系列实验。采用双频等离子体清洗技术进行了这项研究。实验条件是相对于热氧化物的RF /偏置功率和预清洁厚度去除。接触电阻随着直流偏压和预清洁厚度的增加而增加。此外，对于两个150W / 300W和300W / 300W的等离子体功率条件，预清洗等离子体大于200A的晶圆不符合电气规范。用SEM表征硅损失。与没有预清洗的晶片相比，在具有高DC偏压和高的预清洗厚度的预清洗晶片上观察到严重的硅损失。更多的硅损失导致更高的接触链电阻。应使用低直流偏置功率和优化的预清洁厚度去除来优化等离子体预清洁工艺，以消除等离子体损坏。

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