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首页> 外文会议>International Conference on Electrical and Electronics Engineering >A Hardware Efficient Elliptic Curve Accelerator for FPGA Based Cryptographic Applications
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A Hardware Efficient Elliptic Curve Accelerator for FPGA Based Cryptographic Applications

机译：基于FPGA的加密应用的硬件高效椭圆曲线加速器

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The work presents an elliptic curve crypto accelerator to implement scalar multiplication on standardized NIST curve over Galois binary fields by using polynomial basis. The proposed design provides efficient hardware utilization and low power consumption. For this purpose, hybrid finite field multiplier is proposed using standard Karatsuba multiplier and shift-and-add multiplication algorithms. The proposed hybrid finite field multiplier can perform one finite field multiplication in m/2 clock cycles, with m being the key-length. Montgomery algorithm with projective coordinates (Lopez-Dahab) is used for the computation of scalar multiplication. An FSM based control unit is developed, governing the overall operations of proposed accelerator. The proposed architecture has been modeled in Verilog-HDL and implemented up to place and route level using the Xilinx Vivado and ISE design software for various FPGA devices. The achieved results demonstrate the convenience of proposed ECC accelerator for resource constrained embedded systems applications requiring low area and low power hardware.
机译：该工作介绍了一个椭圆曲线加密加速器，通过使用多项式基础来实现在Galois二进制字段上的标准化NIST曲线上的标量乘法。该设计提供了高效的硬件利用率和低功耗。为此目的，使用标准Karatsuba乘法器和移位和添加乘法算法提出混合有限场乘数。所提出的混合有限场乘数可以在M / 2时钟周期中执行一个有限的场乘法，M是键长度。具有投影坐标（Lopez-Dahab）的蒙哥马利算法用于计算标量乘法。开发了一种基于FSM的控制单元，用于提供所提出的加速器的整体操作。该建议的架构已经以Verilog-HDL建模，并使用Xilinx Vivado和ISE设计软件为各种FPGA器件实现了加入和路由级别。实现的结果展示了用于资源受限嵌入式系统应用的建议ECC加速器的便利性，需要低区域和低功耗硬件。

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