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首页> 外文学位 >Design and evaluation of an 'FPGA based' hardware accelerator for elliptic curve cryptography point multiplication.
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Design and evaluation of an 'FPGA based' hardware accelerator for elliptic curve cryptography point multiplication.

机译：用于椭圆曲线密码学点乘法的“基于FPGA”的硬件加速器的设计和评估。

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摘要

Embedded systems are found in many applications in various fields such as defense, communications, industrial automation, and many more. Majority of these applications have security as the primary concern. Cryptography plays an important role in providing data security. Until recently, symmetric key encryption schemes were used for a majority of these applications. Now, however, asymmetric key encryption schemes such as Elliptic curve cryptography are gaining popularity as they require less computational power and memory and are still capable of providing equivalent security when compared to their counterparts such as. Elliptic curve cryptography was first introduced in 1985 and has always been around since. Scalar or point multiplication is the most time- and resource-consuming operation in elliptic curve cryptography. Improving the performance of point multiplication can improve the overall performance of elliptic curve cryptography.;The objective of this research was to design and evaluate a hardware accelerator for the elliptic curve point multiplication operation using Field Programmable Gate Array (FPGA) as the design technology. The performance evaluation was carried out by measuring parameters like maximum frequency of operation, resource utilization, and the speed up achieved by hybrid hardware/software implementation.;There are several algorithms that can be used for computing the product of scalar multiplication, for faster computation the binary non-adjacent form had been chosen for implementation in this thesis. The implementation was carried out using Verilog HDL. A system on programmable chip model (SOPC) was developed using the NIOS II soft processor. The associated firmware with the SOPC model was developed using the NIOS II IDE. The performance evaluation was carried out using the Timing Analyzer, Fitter, and Analysis and Synthesis modules in the Altera Quartus software. The hardware accelerator model has been successfully developed and implemented on the FPGA. The performance parameters for the hardware accelerated model have been evaluated and compared to the generic software implementation model and possible extension to this work has also been provided in this thesis. Performance evaluation of the entire system revealed that the designed system achieved a speed up of approximately 17 times compared to the software only implementation. Logic elements utilized by the Hybrid Implementation (Software -- Hardware combination) were found out to be only 6113 and the throughput per logic element was found out to be 1.484 Kbps thus making the designed system cost efficient, area efficient and faster compared to the software only implementation.
机译：嵌入式系统在国防，通信，工业自动化等各个领域的许多应用中都有发现。这些应用程序中的大多数将安全性作为主要考虑因素。密码学在提供数据安全性方面起着重要作用。直到最近，对称密钥加密方案仍用于大多数此类应用程序。但是，如今，非对称密钥加密方案（例如椭圆曲线密码学）越来越受欢迎，因为它们需要更少的计算能力和内存，并且与之相比，仍能够提供同等的安全性。椭圆曲线密码术于1985年首次引入，此后一直存在。标量或点乘法是椭圆曲线密码学中最耗时和最耗资源的操作。提高点乘法的性能可以改善椭圆曲线密码学的整体性能。本研究的目的是设计和评估使用现场可编程门阵列（FPGA）作为设计技术的椭圆曲线点乘法运算的硬件加速器。性能评估是通过测量最大操作频率，资源利用率以及混合硬件/软件实现所达到的速度等参数来进行的；可以使用几种算法来计算标量乘法的乘积，以便更快地进行计算。本文选择了二进制非相邻形式来实现。该实施是使用Verilog HDL进行的。使用NIOS II软处理器开发了可编程芯片模型系统（SOPC）。与SOPC模型相关的固件是使用NIOS II IDE开发的。使用Altera Quartus软件中的Timing Analyzer，Fitter和Analysis and Synthesis模块进行了性能评估。硬件加速器模型已成功开发并在FPGA上实现。评估了硬件加速模型的性能参数，并将其与通用软件实现模型进行了比较，并且本文还提供了对该工作的可能扩展。整个系统的性能评估表明，与仅软件实现相比，所设计的系统可将速度提高约17倍。混合实现（软件-硬件组合）使用的逻辑元素被发现只有6113，每个逻辑元素的吞吐量被发现为1.484 Kbps，因此与软件相比，设计的系统具有成本效益，面积效率高和速度快的特点。只能执行。

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  • 作者

    Gwalani, Kapil A.;

  • 作者单位

    Tennessee Technological University.;

  • 授予单位 Tennessee Technological University.;
  • 学科 Engineering Electronics and Electrical.
  • 学位 M.S.
  • 年度 2009
  • 页码 115 p.
  • 总页数 115
  • 原文格式 PDF
  • 正文语种 eng
  • 中图分类 地下建筑;
  • 关键词

  • 入库时间 2022-08-17 11:38:24

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