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首页> 外文会议>International Conference on Electrical and Electronics Engineering >A Hardware Efficient Elliptic Curve Accelerator for FPGA Based Cryptographic Applications
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A Hardware Efficient Elliptic Curve Accelerator for FPGA Based Cryptographic Applications

机译：用于基于FPGA的加密应用程序的硬件有效椭圆曲线加速器

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The work presents an elliptic curve crypto accelerator to implement scalar multiplication on standardized NIST curve over Galois binary fields by using polynomial basis. The proposed design provides efficient hardware utilization and low power consumption. For this purpose, hybrid finite field multiplier is proposed using standard Karatsuba multiplier and shift-and-add multiplication algorithms. The proposed hybrid finite field multiplier can perform one finite field multiplication in m/2 clock cycles, with m being the key-length. Montgomery algorithm with projective coordinates (Lopez-Dahab) is used for the computation of scalar multiplication. An FSM based control unit is developed, governing the overall operations of proposed accelerator. The proposed architecture has been modeled in Verilog-HDL and implemented up to place and route level using the Xilinx Vivado and ISE design software for various FPGA devices. The achieved results demonstrate the convenience of proposed ECC accelerator for resource constrained embedded systems applications requiring low area and low power hardware.
机译：这项工作提出了一种椭圆曲线密码加速​​器，以利用多项式在Galois二进制域上的标准化NIST曲线上实现标量乘法。所提出的设计提供了有效的硬件利用率和低功耗。为此，提出了使用标准唐津乘法器和移位加法相乘算法的混合有限域乘法器。所提出的混合有限域乘法器可以在m / 2个时钟周期内执行一个有限域乘法，其中m为密钥长度。具有投影坐标的蒙哥马利算法（Lopez-Dahab）用于计算标量乘法。开发了基于FSM的控制单元，用于控制建议的加速器的整体操作。拟议的架构已在Verilog-HDL中建模，并使用Xilinx Vivado和ISE设计软件针对各种FPGA器件实现了布局和布线级别。所获得的结果证明了所提出的ECC加速器对于需要低面积和低功耗硬件的资源受限的嵌入式系统应用的便利性。

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