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首页> 外文会议>Annual Conference of the IEEE Industrial Electronics Society >Development of FPGA based Hardware-in-the-loop Simulator for RF Cavity Resonator
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Development of FPGA based Hardware-in-the-loop Simulator for RF Cavity Resonator

机译：基于FPGA的RF腔谐振器的FPGA硬件载流模拟器

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This paper presents implementation of a Field Programmable Gate Array (FPGA) emulator for the Low Level Radio Frequency (LLRF) Normal conducting cavity at TRIUMF. Testing waveforms such as phase and amplitude in the cavity on the real hardware can be both difficult and dangerous. To allow testing of the real LLRF system in real time and also to obtain shorter processing time we need to have an effective hardware in the loop simulator of the cavity. Radio frequency (RF) cavity is equivalent to an electrical RLC circuit which acts like a second order filter model, therefore it is possible to emulate the cavity with an analog filter. But when it comes to digital field, the finite word length effect has to be considered and processed carefully. The discrete model of the cavity designed as an IIR bandpass Filter. The SIMULINK and MATLAB model of the cavity and their implementation are presented. An Altera DE4 development board was selected as the emulator of the cavity. And the result of digital designing of the cavity model on FPGA is presented.
机译：本文介绍了在Triumf处的用于低电平射频（LLRF）正常导电腔的现场可编程门阵列（FPGA）仿真器。测试波形如实际硬件上腔中的相位和幅度可能都是困难和危险的。为了允许实时测试真实的LLF系统，并且还可以获得更短的处理时间，我们需要在腔的环路模拟器中具有有效的硬件。射频（RF）腔相当于电动RLC电路，其用作二阶滤波器模型，因此可以用模拟滤波器模拟空腔。但是，当谈到数字字段时，必须仔细考虑和处理有限字的长度效果。设计为IIR带通滤波器的腔的离散模型。介绍了腔的Simulink和Matlab模型及其实现。选择Altera DE4开发板作为腔的仿真器。介绍了FPGA上腔模型的数字设计的结果。

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