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首页> 外文会议>IEEE International Midwest Symposium on Circuits and Systems >HDL to SP conversion containing interconnect effects using SAD matrix
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HDL to SP conversion containing interconnect effects using SAD matrix

机译：HDL到SP转换，使用悲伤矩阵包含互连效应

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This paper introduces a new method to take into account the effects of interconnects in simulations of modern digital circuits. It is possible in this technique to take into account the impact of interconnects in early stages of high level design with no need of layout information. In this method the description of the circuit is modeled as a graph. This graph is shown in a new shape of adjacency matrix which is optimized in terms of number of vertices rather than a regular adjacency matrix. We call this new matrix the sad-mat1. The sad-mat is stored in computer memory by means of linked lists. The algorithm used by the previous work on HDL to SP Conversion was NP-Complete. The proposed method in this paper uses a new algorithm which has complexity O(log n) where n is total number of primitive inputs and outputs and none- primitive nodes in the circuit. This new method has been applied to many standard ISCAS circuits and the output results have shown a significant improvement in terms of running time. The proposed method is implemented as a CAD tool called H2SP. ISCAS circuits are also used to verify the H2SP's algorithm.
机译：本文介绍了一种新方法，以考虑互连在现代数字电路模拟中的影响。在这种技术中可以考虑互连在高级设计的早期阶段的影响，不需要布局信息。在该方法中，电路的描述被建模为图。该图表以新的邻接矩阵形状示出，其在顶点数量而不是常规邻接矩阵的任节中进行了优化。我们称这个新矩阵是SAD-MAT1。 SAD-MAT通过链接列表存储在计算机存储器中。以前的HDL到SP转换使用的算法是NP-Complete。本文中所提出的方法使用具有复杂性O（log n）的新算法，其中n是电路中的原始输入和输出的总数和非原始节点。这种新方法已应用于许多标准ISCAS电路，输出结果显示出运行时间的显着改进。所提出的方法被实现为称为H2SP的CAD工具。 ISCAS电路还用于验证H2SP的算法。

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