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Improving MLC flash performance and endurance with extended P/E cycles

机译：利用扩展的P / E循环提高MLC闪光性能和耐力

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The traditional usage pattern for NAND flash memory is the program/erase (P/E) cycle: the flash pages that make a flash block are all programmed in order and then the whole flash block needs to be erased before the pages can be programmed again. The erase operations are slow, wear out the medium, and require costly garbage collection procedures. Reducing their number is therefore beneficial both in terms of performance and endurance. The physical structure of flash cells limits the number of opportunities to overcome the 1 to 1 ratio between programming and erasing pages: a bit storing a logical 0 cannot be reprogrammed to a logical 1 before the end of the P/E cycle. This paper presents a technique to minimize the number of erase operations called extended P/E cycle. With extended P/E cycles, the flash pages can be programmed many times before the whole flash block needs to be erased, reducing the number of erase operations. We study the applicability of the technique to Multi Level Cell (MLC) NAND flash chips, and present a design and implementation on the OpenSSD prototyping board. The evaluation of our prototype shows that this technique can achieve erase operations reduction as high as 85%, with latency speedups of up to 67%, with respect to a FTL with traditional P/E cycles, and naive greedy garbage collection strategy. Our evaluation leads to valuable insights on how extended P/E cycles can be exploited by future applications.
机译：NAND闪存的传统使用模式是程序/擦除（P / E）周期：使闪存块的闪存页面都按顺序编程，然后在页面可以再次编程之前需要擦除整个闪存块。擦除操作缓慢，磨损介质，并要求昂贵的垃圾收集程序。因此，在性能和耐力方面，减少他们的数量是有益的。闪存单元的物理结构限制了克服编程和擦除页面之间的1至1比率的机会的数量：在P / E循环结束之前，存储逻辑0的比特不能被重新编程到逻辑1。本文介绍了一种最小化称为扩展P / E循环的擦除操作数量的技术。通过扩展的P / E循环，闪存页面可以在需要擦除整个闪存块之前多次编程，减少擦除操作的数量。我们研究了技术对多级单元（MLC）NAND闪存芯片的适用性，并在OpenSSD原型板上提供了设计和实现。我们的原型的评估表明，该技术可以实现高达85％的擦除操作，延迟加速高达67％，相对于具有传统的P / E循环的FTL，以及天真的贪婪垃圾收集策略。我们的评估导致有价值的见解，可以通过未来的应用程序利用延长的P / E循环。

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