Low-voltage current-mode preamplifier based Latch comparator

机译：基于低压电流模式前置放大器的锁存比较器

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This paper presents a low-voltage latch current comparator. The circuit was designed on the basis of current mirror, preamplifier and latch circuits and also various circuit techniques; quasi-floating gate to reduce the input impedance, bulk driven technique for the circuit to be operable under low supply voltage and positive feedback to increase the gain and the overall speed. From the simulation results, which were presented with 0.18 um CMOS technology, the circuit can operate well at the supply voltage of 0.5 volt and the resulting propagation delay time were 2.2 nS and 1.4 nS when the input current differences are 1 uA and 10 uA, respectively. The total power dissipation was 79 uW.

机译：本文提出了一种低压锁存电流比较器。该电路是根据电流镜，前置放大器和锁存电路以及各种电路技术设计的;准浮栅可降低输入阻抗，体驱动技术可使电路在低电源电压和正反馈下工作，以增加增益和总体速度。根据采用0.18 um CMOS技术提出的仿真结果，当输入电流差为1 uA和10 uA时，电路在0.5伏的电源电压下可以很好地工作，并且传播延迟时间分别为2.2 nS和1.4 nS，分别。总功耗为79 uW。

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《International Conference on Electrical Engineering/Electronics, Computer, Telecommunications and Information Technology》|2016年|1-4|共4页
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Thongchai Jankatkit; Varakorn Kasemsuwan;
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关键词
Transistors; Latches; Impedance; Preamplifiers; Time factors; Mirrors; Inverters;

机译：晶体管;锁存器;阻抗;前置放大器;时间因素;镜子;逆变器;

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1. A NEW PREAMPLIFIER BASED LATCHED COMPARATOR WITH RESET CONFIRMATION TRANSISTOR [J] . Seyed Mohammad Alavi, Nabiallah Shiri The mediterranean journal of electronics and communications . 2014,第2期

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2. Design and analysis of a high speed double-tail comparator with isomorphic latch-preamplifier pairs and tail bootstrapping [J] . Rahmani S., Ghaznavi-Ghoushchi M. B. Analog Integrated Circuits and Signal Processing . 2017,第3期

机译：具有同构锁定前置放大器对和尾牵引的高速双尾比较器的设计与分析
3. Low-voltage CMOS current-mode preamplifier: analysis and design [J] . Fei Yuan IEEE transactions on circuits and systems . I , Regular papers . 2006,第1期

机译：低压CMOS电流模式前置放大器：分析和设计
4. Low-voltage current-mode preamplifier based Latch comparator [C] . Thongchai Jankatkit, Varakorn Kasemsuwan International Conference on Electrical Engineering/Electronics, Computer, Telecommunications and Information Technology . 2016

机译：基于低压电流模式前置放大器的锁存器比较器
5. Low-power high-speed low-offset fully dynamic CMOS latched comparator [D] . Jeon, HeungJun. 2010

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6. Design of High Speed and Low Offset Dynamic Latch Comparator in 0.18 µm CMOS Process [O] . Labonnah Farzana Rahman, Mamun Bin Ibne Reaz, Chia Chieu Yin, 2010

机译：0.18 µm CMOS工艺中的高速，低偏移动态锁存比较器的设计
7. Analysis and design of preamplifier-latch comparator for high accuracy switched-capacitor pipelined ADC [O] . 李扬, 吴金荣, 刘磊, 2012

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Low-voltage current-mode preamplifier based Latch comparator

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