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首页> 外文期刊>The mediterranean journal of electronics and communications >A NEW PREAMPLIFIER BASED LATCHED COMPARATOR WITH RESET CONFIRMATION TRANSISTOR
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A NEW PREAMPLIFIER BASED LATCHED COMPARATOR WITH RESET CONFIRMATION TRANSISTOR

机译：一种带有复位确认晶体管的新型基于前置放大器的锁存比较器

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摘要

A new high performance preamplifier based latched comparator is proposed. By adding a reset confirmation transistor in parallel to the reset transistor in class AB latched comparator, a new comparator is created. In one forth of a period, the added transistor is ON and the reset time will be decreased, therefore maximum working frequency will increase. Reset confirmation transistor allows the main reset transistor to have a very smaller size than conventional comparators, thus decreases noise at the output nodes and increases decision accuracy. The circuit is simulated using HSPICE based on 90nm CMOS technology, BSIM4 (level 54), version 4.4, at 25° centigrade with 10fF capacitance loads in outputs. Supply voltage was set to 1 Volt. Simulation results reveal that although the comparator has quite large area, yet it has excellent performance, maximum operating frequency is 3.125GHz, input referred offset voltage is 13.8mV and power consumption is 184.3μW. Reset time in the proposed circuit is 12.5% of a clock period while in the conventional class AB latched comparators are 37.5%. High speed, fast reset, low noise, low power consumption and nearly low offset voltage make this comparator suitable for global applications like signal edge detection, trigger interrupts and ADCs applications, especially flash ADCs.
机译：提出了一种新的基于高性能前置放大器的锁存比较器。通过在AB类锁存比较器中与复位晶体管并联添加一个复位确认晶体管，可以创建一个新的比较器。在一个周期的四分之一中，添加的晶体管处于导通状态，复位时间将减少，因此最大工作频率将增加。复位确认晶体管使主复位晶体管的尺寸比传统的比较器小得多，从而降低了输出节点的噪声并提高了决策精度。使用基于90nm CMOS技术的HSPICE（BSIM4（54级），版本4.4）在25°C且输出端具有10fF电容负载的情况下对电路进行仿真。电源电压设置为1伏。仿真结果表明，该比较器虽然面积较大，但性能优良，最大工作频率为3.125GHz，输入参考失调电压为13.8mV，功耗为184.3μW。所提出的电路中的复位时间为时钟周期的12.5％，而传统的AB类锁存比较器为37.5％。高速，快速复位，低噪声，低功耗和接近低的失调电压使该比较器适用于全局应用，例如信号边沿检测，触发中断和ADC应用，尤其是闪存ADC。

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