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A novel design of a Dual Functionality Read-Write driver for SRAM

机译：用于SRAM的双功能读写驱动程序的新颖设计

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摘要

Memory systems like Static Random Access Memories (SRAM) and Non Volatile Memories (NVM) thrive on area and power efficient designs. This paper presents a novel and a power proficient design of a Dual Functionality Read-Write (DFR-W) driver for SRAM sub-system. This design is integrated with a memory sub-system with an operating frequency of 1GHz in CMOS 65nm technology. It is then compared with a conventional memory architecture on grounds of power, area, leakage and speed of operation for varied memory capacities. DFR-W depicts a reduction of up to 35.58% in latching delay and of about 14% in writing time as compared to the conventional memory architecture. For the new design, there is a drastic decline in leakage current when the device is in hold mode. In DFR-W driver, leakage reduces to about 8.0844nA as compared to 22.833nA in the conventional design. The complete memory architecture with DFR-W driver shows a reduction of up to 6% in the power dissipation as compared to the conventional design. The proposed design performance is found way superior and efficient in terms of speed and power.
机译：像静态随机存取存储器（SRAM）和非易失性存储器（NVM）等内存系统在区域和功率高效设计上茁壮成长。本文介绍了用于SRAM子系统的双功能读写（DFR-W）驱动程序的新颖和动力精通设计。该设计与内部系统集成在CMOS 65NM技术中具有1GHz的工作频率。然后将其与传统的存储器架构相比，在电力，面积，泄漏和操作速度的地面，用于变化的存储容量。 DFR-W与传统的内存架构相比，在锁定延迟中减少了高达35.58％的锁定延迟，并且在书写时间中约14％。对于新设计，设备处于保持模式时，漏电流存在急剧下降。在DFR-W驱动程序中，泄漏减少至约8.0844NA，而传统设计中的22.833NA相比。与传统设计相比，具有DFR-W驱动程序的完整内存架构显示出功耗最高可达6％的减少。在速度和功率方面，所提出的设计性能是优越和高效的。

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