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Comparative analysis of hybrid Magnetic Tunnel Junction and CMOS logic circuits

机译：混合磁隧道结和CMOS逻辑电路的比较分析

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摘要

Spin Transfer Torque (STT) is a promising technology for storage in which the information is stored in the form of magnetic orientation of a Magnetic Tunnel Junction (MTJ) rather than electric charge. Besides memory applications, this technology is promising for non-volatile reconfigurable logic design. The major challenge in realizing this technology is the power and performance overhead associated with reading the state of MTJs (high and low resistance states) and converting it into high and low voltages for interface to next stage circuits. In this paper, methods are proposed to reduce this overhead by MTJ resistance optimization at the device level and mapping multiple low fan-in logic gates into a STT-based Look Up Table (STT-LUT) at the circuit level. The paper demonstrates that by optimally mapping logic gates to STT-LUTs, the power and performance overhead of a reconfigurable design can be reduced to become competitive with a full-custom design. Our results on an arithmetic benchmark circuit shows that by optimal logic gate mapping into STT-LUTs, the power and performance of the design is improved by 65% and 54%, respectively, compared to the design where each individual logic gates is replaced by an STT-LUT.
机译：旋转转移扭矩（STT）是用于存储的有希望的技术，其中信息以磁隧道结（MTJ）的磁取向而不是电荷的形式存储。除了内存应用程序外，该技术对于非易失性可重新配置逻辑设计是有前途的。实现这一技术的主要挑战是与读取MTJS（高电平和低阻状态）的状态，并将其转换为与下一个阶段电路接口的高电压和低电压相关联的电力和性能开销。在本文中，提出了通过在设备级别的MTJ电阻优化来减少该开销，并在电路电平的基于STT的查找表（STT-LUT）中将多个低风扇逻辑门映射到基于STT的查找表（STT-LUT）中的映射。本文演示了，通过最佳地将逻辑门映射到STT-LUT，可以减少可重新配置设计的功率和性能开销，以使具有全定制设计具有竞争力。我们对算术基准电路的结果表明，通过最佳逻辑门映射到STT-LUT，与设计相比，设计的功率和性能分别提高了65％和54％，其中每个单独的逻辑门被替换stt-lut。

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