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Performance optimization and power efficiency in 3D IC with buffer insertion scheme

机译：具有缓冲插入方案的3D IC的性能优化和功率效率

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We present a new scheme of buffer implementation in through-silicon via (TSV) based 3D circuits at early layout design stage for total delay minimization. For optimal buffer insertion at floorplanning level, it is important to incorporate more accurate and realistic estimation of interconnect delay and power. Early prediction of delay and power leads to better design decisions, overall timing closure and design convergence. The proposed buffer insertion scheme is integrated within the nets-to-TSVs assignment process, therefore considers the actual TSV position during buffer planning around TSVs. This method significantly minimizes signal degradation across TSVs while also avoiding excessive usage of buffers. We demonstrate that the choice of nominal wire length, which is a fixed interval between adjacent buffers, plays a critical role in the delay and power prediction of buffered interconnects. The nominal wirelength in our approach is represented by a multiplicity of the TSV equivalent wire length, which effectively models the TSV RC delay contribution to delay of a net. We compare the efficiency of our proposed scheme with existing buffer insertion techniques in 3D circuits. The power efficiency achieved by 3D circuit incorporating the proposed buffer insertion scheme is shown to be 38% higher than in 2D implementation of the same circuit.
机译：在早期布局设计阶段，我们在基于硅通孔（TSV）3D电路中的缓冲器实现的新方案，用于总延迟最小化。为了在平面平面级别的最佳缓冲区插入，重要的是融合更准确和更现实的互连延迟和功率的估计。早期预测延迟和电力导致更好的设计决策，整体时序闭合和设计汇聚。所提出的缓冲区插入方案集成在网络到TSVS分配过程中，因此在TSV周围的缓冲区规划期间考虑实际的TSV位置。该方法显着最大限度地减少了TSV的信号劣化，同时还避免过度使用缓冲器。我们证明了标称线长度的选择，即相邻缓冲区之间的固定间隔，在缓冲互连的延迟和功率预测中起着关键作用。我们方法中的标称Wirelengge由TSV等效线长度的多个，这有效地模拟了TSV RC延迟贡献以延迟网络。我们将所提出的方案的效率与3D电路中的现有缓冲插入技术进行比较。通过结合所提出的缓冲器插入方案的3D电路实现的功率效率显示为比同一电路的2D实施方式高出38％。

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