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A novel configurable VLSI architecture design of window-based image processing method

机译：基于窗口的图像处理方法的新型可配置VLSI架构设计

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Most window-based image processing architecture can only achieve a certain kind of specific algorithms, such as 2D convolution, and therefore lack the flexibility and breadth of application. In addition, improper handling of the image boundary can cause loss of accuracy, or consume more logic resources. For the above problems, this paper proposes a new VLSI architecture of window-based image processing operations, which is configurable and based on consideration of the image boundary. An efficient technique is explored to manage the image borders by overlapping and flushing phases at the end of row and the end of frame, which does not produce new delay and reduce the overhead in real-time applications. Maximize the reuse of the on-chip memory data, in order to reduce the hardware complexity and external bandwidth requirements. To perform different scalar function and reduction function operations in pipeline, this can support a variety of applications of window-based image processing. Compared with the performance of other reported structures, the performance of the new structure has some similarities to some of the structures, but also superior to some other structures. Especially when compared with a systolic array processor CWP, this structure at the same frequency of approximately 12.9% of the speed increases. The proposed parallel VLSI architecture was implemented with SIMC 0.18-μm CMOS technology, and the maximum clock frequency, power consumption, and area are 125Mhz, 57mW, 104.8K Gates, respectively, furthermore the processing time is independent of the different window-based algorithms mapped to the structure.
机译：大多数基于窗口的图像处理体系结构只能实现某种特定的算法，例如2D卷积，因此缺乏应用的灵活性和广度。此外，对图像边界的不正确处理可能会导致精度损失或消耗更多的逻辑资源。针对上述问题，本文提出了一种新的基于窗口的图像处理操作的VLSI体系结构，该体系结构是可配置的，并且考虑了图像边界。探索了一种有效的技术，通过在行末和帧末的重叠和冲洗阶段来管理图像边界，这不会产生新的延迟并减少实时应用程序中的开销。最大限度地重用片上存储器数据，以降低硬件复杂性和外部带宽要求。为了在流水线中执行不同的标量函数和归约函数操作，这可以支持基于窗口的图像处理的各种应用。与其他已报告结构的性能相比，新结构的性能与某些结构有一些相似之处，但也优于其他一些结构。特别是与脉动阵列处理器CWP相比时，这种结构在大约12.9％的相同频率下增加了速度。拟议的并行VLSI架构采用SIMC0.18-μmCMOS技术实现，最大时钟频率，功耗和面积分别为125Mhz，57mW和104.8K Gates，此外，处理时间与不同的基于窗口的算法无关映射到结构。

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