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首页> 外文会议>IEEE International Conference on Smart Technologies >A Customizable DDR3 SDRAM Controller Tailored for FPGA-Based Data Buffering Inside Real-Time Range-Doppler Radar Signal Processing Back Ends
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A Customizable DDR3 SDRAM Controller Tailored for FPGA-Based Data Buffering Inside Real-Time Range-Doppler Radar Signal Processing Back Ends

机译：可定制的DDR3 SDRAM控制器，用于基于FPGA的数据缓冲，内部实时范围 - 多普勒雷达信号处理后端

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摘要

High resolution commercial radars which feature arrays of transmit and receive antennas and that rely on unambiguous range-Doppler signal processing with hard real-time constraints require fast memories to store intermediate results. Typical radar data matrices can occupy up to a gigabyte of space. A custom DRAM controller tailored for digital radar back ends and software-defined radars is presented. It is implemented on an FPGA and supports data buffering between the two FFT stages inside a two-dimensional spectral analysis system. In parallel, it allows the remaining part of the SDRAM to be used as a virtual FIFO buffer for the output results. Experimental tests have shown that when both pairs of the proposed memory controller's ports are accessed simultaneously, their joint data throughput is within 10% of the gross theoretical limit for the utilized DDR3 module.
机译：高分辨率商业雷达，具有发射和接收天线的阵列，并且依赖于具有硬实时约束的明确范围 - 多普勒信号处理需要快速存储来存储中间结果。典型的雷达数据矩阵可以占用千兆字节的空间。介绍了用于数字雷达后端的自定义DRAM控制器和软件定义的雷达。它在FPGA上实现，并支持二维光谱分析系统内的两个FFT级之间的数据缓冲。并行地，它允许SDRAM的剩余部分用作输出结果的虚拟FIFO缓冲区。实验测试表明，当同时访问两个提出的存储器控​​制器的端口时，它们的联合数据吞吐量位于所使用的DDR3模块的毛理论限制的10％以内。

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