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首页> 外文会议>IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems >Reliable Hardware Architectures for the Third-Round SHA-3 Finalist Grostl Benchmarked on FPGA Platform
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Reliable Hardware Architectures for the Third-Round SHA-3 Finalist Grostl Benchmarked on FPGA Platform

机译：在FPGA平台上基准测试的第三轮SHA-3 Finalist Grostl的可靠硬件架构

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The third round of competition for the SHA-3 candidates is ongoing to select the winning function in 2012. Although much attention has been devoted to the performance and security of these candidates, the approaches for increasing their reliability have not been presented to date. In this paper, for the first time, we propose a high-performance scheme for fault detection of the SHA-3 round-three candidate Grostl which is inspired by the Advanced Encryption Standard (AES). We propose a low-overhead fault detection scheme by presenting closed formulations for the predicted signatures of different transformations of this SHA-3 third-round finalist. These signatures are derived to achieve low overhead and include one or multi-bit parities and byte/word-wide predicted signatures. The proposed reliable hardware architectures for Grostl are implemented on Xilinx Virtex-6 FPGA family to benchmark their hardware and timing characteristics. The results of our evaluations show high error coverage and acceptable overhead for the proposed scheme.
机译：SHA-3候选人的第三轮竞争正在持续选择2012年的获胜功能。虽然这些候选人的表现和安全致力于众多关注，但迄今尚未提出增加其可靠性的方法。本文首次提出了一种高性能方案，用于对SHA-3轮三次候选Grostl的故障检测，这是由先进的加密标准（AES）的启发。我们提出了一种低开销故障检测方案，通过呈现该SHA-3第三轮决赛选项的不同转型的预测签名。导出这些签名以实现低开销，并包括一个或多个间隔和字节/字范围预测签名。 Grostl的建议可靠的硬件架构是在Xilinx Virtex-6 FPGA系列上实现的，以基准其硬件和时序特性。我们的评估结果显示了拟议计划的高误差覆盖范围和可接受的开销。

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