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首页> 外文会议>Electronics, Circuits and Systems, 2001. ICECS 2001. The 8th IEEE International Conference on >ESD test methods on integrated circuits: an overview
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ESD test methods on integrated circuits: an overview

机译：集成电路上的ESD测试方法：概述

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摘要

ESD phenomenon has become a serious problem for IC products fabricated by deep-submicron CMOS technologies. To qualify the ESD immunity of IC products, there are some test methods and standards developed by certain organizations, such as ESDA, AEC, EIA/JEDEC, and MIL-STD organizations. ESD events have been classified into 4 models, which are HBM, MM, CDM, and SDM. There are 4 modes of pin combinations for ESD zapping on the IC pins, which are specified as (1) pin-to-VSS, (2) pin-to-VDD, (3) pin-to-pin, and (4) VDD-to-VSS. All the test methods are designed to evaluate the ESD immunity of IC products. The zap number, zap interval, and sample size are all well defined in the related industrial standards. This paper provides an overview among ESD test methods on IC products. In general, the commercial IC products are requested to sustain at least 2-kV HBM, 200-V MM, and 1-kV CDM ESD stresses.
机译：对于通过深亚微米CMOS技术制造的IC产品，ESD现象已成为一个严重的问题。为了验证IC产品的ESD免疫力，某些组织（例如ESDA，AEC，EIA / JEDEC和MIL-STD组织）制定了一些测试方法和标准。 ESD事件已分为4个模型，分别是HBM，MM，CDM和SDM。 IC引脚上有4种用于ESD快速切换的引脚组合模式，分别指定为（1）引脚至VSS，（2）引脚至VDD，（3）引脚至引脚和（4） VDD至VSS。所有测试方法均旨在评估IC产品的ESD抗扰性。跳变次数，跳变间隔和样本大小在相关的工业标准中都有很好的定义。本文概述了IC产品上的ESD测试方法。通常，要求商用IC产品承受至少2kV HBM，200V MM和1kV CDM ESD应力。

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