首页> 外文会议>Electronics, Circuits and Systems, 2001. ICECS 2001. The 8th IEEE International Conference on >Maximum power supply noise estimation in VLSI circuits using multimodal genetic algorithms
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Maximum power supply noise estimation in VLSI circuits using multimodal genetic algorithms

机译:使用多模态遗传算法的VLSI电路中的最大电源噪声估计

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This paper presents a genetic algorithm (GA) based method for finding the maximum voltage drop in the power bus of digital VLSI circuits. The worst-case voltage drop at a specified node in the power bus is defined as the fitness value for different input-vector pairs. A gate-level simulator and a sparse linear solver are applied to compute the fitness value. A sharing technique is applied to find the global optima accurately and rapidly. Comparisons with input-independent simulations for circuits extracted from layouts are used to validate our approach.
机译:本文提出了一种基于遗传算法(GA)的方法来查找数字VLSI电路的电源总线中的最大压降。将电源总线中指定节点处的最坏情况下的压降定义为不同输入矢量对的适应度值。应用门级模拟器和稀疏线性求解器来计算适应度值。应用共享技术可以准确快速地找到全局最优值。与从布局中提取的电路的与输入无关的仿真的比较用于验证我们的方法。

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