As technology advances towards 45nm node and beyond, optical lithography faces increased challenges and resolution enhancement techniques (RET) are imperative for multiple process layers and poly-silicon gate layer in particular. With RET implementation, and optical proximity correction (OPC) techniques, the mask layout deviates further away from design intended layout. For an OPC decorated design database, it is important that before mask making, the OPC is verified that it is design related defects free and provides reasonable process window for a given process to ensure manufacturability. For poly-silicon gate layer, due to tight CD control requirement, the demand for accurate lithography process simulation is even greater. As hyper-NA immersion exposure systems become available, accurate resist image computation considering mask topography effects and partial polarized illumination on poly-silicon gate layers through process window is a necessary. In this work, we will show simulation results of DesignScan on an advanced poly-silicon gate layer using a logic based customer database. Active layer database is used to separate poly-silicon gate regions and poly-silicon wire regions. Sensitive CD and edge placement error (EPE) detectors are used to identify design related defects through the lithography process window. The detector sensitivities can be adjusted based on feature sizes and their geometry (gate of different targets or wires, corners, and line ends). This customization of geometry classification and detector sensitivity is critical to achieve desired through process window inspections. With this capability process window inspections will show how CD/EPE changes as functions of exposure dose and defocus with fast results and efficient review and disposition. Accurate process window assessment using CD variation is obtained.
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