首页> 外文会议>Asia-Pacific Microwave Conference >A 7 GHz Differential 4-Stage Programmable Equalizer with Hybrid Continuous-Time/Discrete-Time Architecture in 28 nm CMOS

【24h】

A 7 GHz Differential 4-Stage Programmable Equalizer with Hybrid Continuous-Time/Discrete-Time Architecture in 28 nm CMOS

机译：一个7 GHz差分4级可编程均衡器，其中包含28 nm CMOS的混合连续时间/离散时间架构

获取原文

页面导航

摘要
著录项
相似文献
相关主题

摘要

This paper presents a programmable wideband equalizer with hybrid Continuous-Time (CT)/Discrete-Time (DT) architecture. Unlike the conventional hybrid CT/DT LPF, the proposed circuit enables large compensation level (CL) at high peaking frequencies. A prototype has been fabricated in 28 nm CMOS. The proposed equalizer achieves up to 7 GHz peaking frequency with more than 10dB of CL. In addition, it offers capacitance ratio ( C ratio) and clock frequency (fCK) programmability. The proposed equalizer occupies 0.061 mm^{2 of active area.}

机译：本文介绍了具有混合连续时间（CT）/离散时间（DT）架构的可编程宽带均衡器。与传统的混合CT / DT LPF不同，所提出的电路在高峰值频率下实现大的补偿水平（CL）。原型已在28 nm CMOS中制造。所提出的均衡器可实现高达7个GHz峰值频率，超过10dB的CL。此外，它提供电容比（C比率）和时钟频率（FCK）可编程性。所提出的均衡器占0.061毫米^{2 活跃区域。}

著录项

来源
《Asia-Pacific Microwave Conference》|2018年|814p|共3页
会议地点
作者
Yohei Morishita; Junji Sato; Koji Takinami; Kazuaki Takahashi;
展开▼
作者单位

展开▼
会议组织
原文格式 PDF
正文语种
中图分类 TN015-53;
关键词
Automotive engineering; Companies; Urban areas;

机译：汽车工程;公司;城市地区;

相似文献

外文文献
中文文献
专利

1. Analysis and Design of a Power-Scalable Continuous-Time FIR Equalizer for 10 Gb/s to 25 Gb/s Multi-Mode Fiber EDC in 28 nm LP CMOS [J] . Mammei E., Loi F., Radice F., Solid-State Circuits, IEEE Journal of . 2014,第12期

机译：用于28纳米LP CMOS的10 Gb / s至25 Gb / s多模光纤EDC的功率可扩展连续时间FIR均衡器的分析和设计
2. A 4-stage 60-GHz low-noise amplifier in 65-nm CMOS with body biasing to control gain, linearity, and input matching [J] . Hooman Rashtian, Shahriar Mirabbasi, Thierry Taris, Analog Integrated Circuits and Signal Processing . 2012,第3期

机译：一个采用65nm CMOS的4级60GHz低噪声放大器，具有偏置功能，可控制增益，线性度和输入匹配
3. A 4-stage 60-GHz low-noise amplifier in 65-nm CMOS with body biasing to control gain, linearity, and input matching [J] . Hooman Rashtian, Shahriar Mirabbasi, Thierry Taris, Analog Integrated Circuits and Signal Processing . 2012,第3期

机译：一个采用65nm CMOS的4级60GHz低噪声放大器，具有身体偏置功能，以控制增益，线性度和输入匹配
4. A 7 GHz Differential 4-Stage Programmable Equalizer with Hybrid Continuous-Time/Discrete-Time Architecture in 28 nm CMOS [C] . Yohei Morishita, Junji Sato, Koji Takinami, Asia-Pacific Microwave Conference . 2018

机译：具有28 nm CMOS连续/离散时间混合架构的7 GHz差分4阶可编程均衡器
5. A 2.4GHz fully differential RF sampling front end in 0.18 μm CMOS process [D] . Wang, Wei. 2009

机译：一个2.4GHz全差分RF采样前端在0.18μmCMOS过程中
6. Comparative Analyses of Phase Noise in 28 nm CMOS LC Oscillator Circuit Topologies: Hartley Colpitts and Common-Source Cross-Coupled Differential Pair [O] . Ilias Chlis, Domenico Pepe, Domenico Zito -1

机译：28 nm CMOS LC振荡器电路拓扑中的相位噪声的比较分析：HartleyColpitts和共源交叉耦合差分对
7. 30 GHz Adaptive Receiver Equalization Design Using 28 nm CMOS Technology [O] . Gustavo Tostado Villanueva -1

机译：30 GHz自适应接收器均衡设计使用28 nm CMOS技术
8. Analog 65/130 nm CMOS 5 GHz Sub-Arrays with ROACH-2 FPGA Beamformers for Hybrid Aperture-Array Receivers. [R] . Ariyarathna, V., Udayanga, N., Madanayake, A., 2017

机译：具有ROaCH-2 FpGa波束形成器的模拟65/130 nm CmOs 5 GHz子阵列，用于混合孔径阵列接收器。

A 7 GHz Differential 4-Stage Programmable Equalizer with Hybrid Continuous-Time/Discrete-Time Architecture in 28 nm CMOS

摘要

著录项

相似文献

相关主题

期刊订阅