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Using Java optimized processor as an intellectual property core beside a RISC processor in FPGA

机译：使用Java优化的处理器作为FPGA中RISC处理器之外的知识产权核心

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Advances in computer technology have made this technology part of everyone's daily life. This in turn has created a demand for various applications to run on different machines. Java programming language was introduced to address this demand. However, to execute the Java programs, the computers must have a machine, called Java Virtual Machine (JVM) that translates its generic codes to machine-specific instructions. Traditionally, JVMs have been implemented in software. This is primarily due to the inherent flexibility of software. However, software JVMs often suffer from their lower speed and memory overhead. Consequently, some efforts have been put into hardware implementations of a JVM. These hardware implementations were not safe from those problems as well. In this paper, a new architecture for hardware implementation of Java Virtual Machine is proposed. This architecture mitigates the problems that hardware implementations of Java Virtual Machine typically have. The proposed architecture is appropriate for designers who use FPGAs as their development platform, or use IP cores in their designs.

机译：计算机技术的进步使得每个人的日常生活的一部分。这又创造了对不同机器运行的各种应用程序的需求。介绍了Java编程语言以解决这一需求。但是，要执行Java程序，计算机必须具有一台机器，称为Java虚拟机（JVM），将其通用代码转换为特定于机器的指令。传统上，JVM已在软件中实现。这主要是由于软件的固有灵活性。但是，软件JVM经常遭受其较低的速度和内存开销。因此，一些努力已经投入了JVM的硬件实现。这些硬件实现也不是安全的那些问题。在本文中，提出了一种新的Java虚拟机硬件实现架构。此架构减轻了Java虚拟机的硬件实现通常具有的问题。拟议的架构适用于使用FPGA作为其开发平台的设计者，或者在其设计中使用IP核心。

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《IEEE East-West Design Test Symposium》|2014年|1-6|共6页
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Khazaee Mohammad Erfan; Hoseinzadeh Shima;
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Java; field programmable gate arrays; microprocessor chips; program interpreters; reduced instruction set computing; virtual machines; FPGA; IP cores; JVM architecture; Java optimized processor; Java programming language; Java virtual machine; RISC processor; generic code translation; hardware implementation; intellectual property core; machine-specific instructions; Central Processing Unit; Computer architecture; Hardware; Java; Reduced instruction set computing; Virtual machining; Bytecode; Bytecode to Native Instruction Translator; Hardware JVM; JOP; Java Optimized Processor; Native Code; Native Instruction;

机译：Java;现场可编程门阵列;微处理器芯片;程序解释器;精简指令集计算;虚拟机; FPGA; IP核; JVM架构; Java优化的处理器; Java编程语言; Java虚拟机; RISC处理器;通用代码转换;硬件实现;知识产权核心;机器专用指令;中央处理单元;计算机体系结构;硬件; Java;精简指令集计算;虚拟加工;字节码;到本机指令转换器的字节码;硬件JVM; JOP; Java优化处理器;本机代码;本机指令;

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专利

1. FPGA prototyping of a RISC processor core for embedded applications [J] . Gschwind M., Salapura V., Maurer D. IEEE transactions on very large scale integration (VLSI) systems . 2001,第2期

机译：针对嵌入式应用的RISC处理器内核的FPGA原型
2. RVCoreP: An Optimized RISC-V Soft Processor of Five-Stage Pipelining [J] . Hiromu MIYAZAKI, Takuto KANAMORI, Md Ashraful ISLAM, IEICE transactions on information and systems . 2020,第12期

机译：RVCOREP：五级流水线的优化RISC-V软处理器
3. FPGA configuration of an alloyed correlated branch predictor used with RISC processor for educational purposes [J] . Hadeel SH. Mahmood International Journal of Electrical and Computer Engineering . 2021,第1期

机译：用于RISC处理器的合金相关分支预测器的FPGA配置用于教育目的
4. Using Java optimized processor as an intellectual property core beside a RISC processor in FPGA [C] . Khazaee Mohammad Erfan, Hoseinzadeh Shima East-West Design Test Symposium . 2014

机译：使用Java优化处理器作为FPGA的RISC处理器旁边的知识产权核心
5. A table look-up pipelined multiplication-accumulation co-processor for H.264, and, An intellectual property authentication scheme for FPGA through watermarking techniques. [D] . Xiao, Xiang. 2006

机译：用于H.264的查表流水线乘法累加协处理器，以及通过水印技术用于FPGA的知识产权认证方案。
6. A Real-Time Marker-Based Visual Sensor Based on a FPGA and a Soft Core Processor [O] . Hilal Tayara, Woonchul Ham, Kil To Chong 2016

机译：基于FPGA和软核处理器的基于标记的实时视觉传感器
7. Design and Implementation of Dual Core and Quad Core Processor in Vertex 6 FPGA Using Pipelined RISC Architecture [O] . Mr. Rakesh M R 2018

机译：双核和四核处理器在顶点6 FPGA中使用流水录RISC架构的设计与实现
8. Performance evaluation of the IBM RISC System/6000: Comparison of an optimized scalar processor with two vector processors. [R] . Simmons, M. L., Wasserman, H. J. 1990

机译：IBm RIsC system / 6000的性能评估：优化的标量处理器与两个矢量处理器的比较。

Using Java optimized processor as an intellectual property core beside a RISC processor in FPGA

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