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Combinational part structure simplification of fully delay testable sequential circuit

机译：完全延迟可测试时序电路的组合零件结构简化

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The method of a sequential circuit design based on using mixed description of a circuit behavior has been developed by us earlier. The method provides fully delay testability of a combinational part of a sequential circuit. It is oriented to cut down the path lengths of the obtained circuits. In this paper the possibilities of a simplification of combinational parts of the sequential circuits are considered. They are based on using corrected Free BDDs instead of ROBDDs and factorizing monotonous products. Some experimental results are given.

机译：基于使用电路行为的混合描述的顺序电路设计的方法已经提前开发。该方法提供顺序电路的组合部分的完全延迟可测试性。它定向为减小所获得的电路的路径长度。在本文中，考虑了顺序电路的组合部分的简化的可能性。它们是基于使用纠正的免费BDD而不是ROBDD和整理单调产品。给出了一些实验结果。

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《IEEE East-West Design Test Symposium》|2014年|1-5|共5页
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Matrosova A.; Mitrofanov E.; Roumjantseva E.;
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logic design; logic testing; sequential circuits; ROBDD; corrected free BDD; delay testability; delay testable sequential circuit; sequential circuit design; Boolean functions; Circuit faults; Data structures; Delays; Logic gates; Robustness; Sequential circuits;

机译：逻辑设计;逻辑测试;时序电路; ROBDD;校正后的自由BDD;延迟可测试性;可延迟测试的时序电路;时序电路设计;布尔函数;电路故障;数据结构;延迟;逻辑门;稳健性;时序电路;

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专利

1. A new class of sequential circuits with combinational test generation complexity for path delay faults [J] . Shunjiro Miwa, Satoshi Ohtake, Hideo Fujiwara 電子情報通信学会技術研究報告. フォ-ルトトレラントシステム . 2000,第620期

机译：一种新的顺序电路，具有用于路径延迟故障的组合测试生成复杂性
2. A new class of sequential circuits with combinational test generation complexity for path delay faults [J] . Shunjiro Miwa, Satoshi Ohtake, Hideo Fujiwara 電子情報通信学会技術研究報告. フォ-ルトトレラントシステム . 2000,第620期

机译：一种新的顺序电路，具有用于路径延迟故障的组合测试生成复杂性
3. Fuzzy delay model based fault simulator for crosstalk delay fault test generation in asynchronous sequential circuits [J] . Jayanthy S., Bhuvaneswari M. C. Sadhana: Academy Proceedings in Engineering Science . 2015,第1期

机译：基于模糊延迟模型的故障模拟器，用于异步时序电路中的串扰延迟故障测试生成
4. Combinational part structure simplification of fully delay testable sequential circuit [C] . Matrosova A., Mitrofanov E., Roumjantseva E. East-West Design Test Symposium . 2014

机译：组合部分结构完全延迟可测试的顺序电路简化
5. Efficient and high quality delay testing for combinational and scan circuits. [D] . Shao, Yun. 2002

机译：组合电路和扫描电路的高效和高质量延迟测试。
6. Delayed Sequential Co-Delivery of Gefitinib and Doxorubicin for Targeted Combination Chemotherapy [O] . Zilan Zhou, Mina Jafari, Vishnu Sriram, -1

机译：吉非替尼和阿霉素在靶向联合化疗中的延迟顺序分娩
7. Model checker-based delay fault testing of sequential circuits [O] . Takan Savaş, Güler Berkin, Ayav Tolga 2015

机译：基于模型检查器的时序电路延迟故障测试
8. Delay Test Generation for Synchronous Sequential Circuits. [R] . Devadas, S. 1989

机译：同步时序电路的延迟测试生成。

Combinational part structure simplification of fully delay testable sequential circuit

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