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The impact of metal hard-mask AIO etch on BEOL electrical performance

机译：金属硬掩模AIO蚀刻对BEOL电气性能的影响

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摘要

In advanced CMOS technology nodes with Cu/low-k interconnect, as Cu line CD continues being scaled, the back-end-of-line (BEOL) electrical performance significantly impacts the chip operation speed by total RC (Resistance and Capacitance) delay. The resistance includes metal sheet resistance (RS) and via contact resistance (RC), while the capacitance includes inter metal and intra metal capacitance. Metal sheet resistance is always coupled with intra metal capacitance, so trench CD and profile dominate both metal resistance and intra metal capacitance if low-k damage is well controlled. The trench CD and profile associated with lower RC delay are proposed. If gap filling capability is considered, tapered trench profile is preferred and then metal HM CD and film thickness need be optimized to meet the RC delay target. The contact resistance of via is dominated by via contact area. Via bottom CD and trench top CD decide the contact area together and both of them are critical for KV RC reduction. Via chamfer profile effect on via resistance is insignificant. Partial via etch depth plays totally different role in KV RC on two different kinds of film stack. The mechanism of this phenomenon is addressed. Such complex correlation between via and trench is investigated in this paper by means of electrical performance testing, meanwhile the impact of AIO etch on BEOL electrical performance is revealed correspondingly.
机译：在具有Cu / Low-K互连的高级CMOS技术节点中，随着Cu线CD继续缩放，线路端部（BEOL）电性能通过总RC（电阻和电容）延迟显着影响芯片运行速度。电阻包括金属薄层电阻（RS）和通过接触电阻（RC），而电容包括金属间和金属型电容。金属薄层电阻始终与金属内电容耦合，因此如果低k损坏受到良好控制，则沟槽CD和曲线占据金属阻力和金属内金属电容。提出了与较低RC延迟相关的沟槽CD和曲线。如果考虑间隙填充能力，则优选锥形沟槽曲线，然后优化金属HM CD和膜厚度以满足RC延迟目标。通孔的接触电阻通过通孔接触区域为主。通过底部CD和沟槽顶部CD决定将接触区域一起决定，两者都对KV RC减少至关重要。通过倒角轮廓效应对通过电阻无足轻重。部分通过蚀刻深度在两种不同种类的胶卷堆栈上在KV RC中发挥完全不同的作用。解决了这种现象的机制。通过电性能测试在本文中研究了通孔和沟槽之间的这种复杂相关性，同时相应地揭示了AIO蚀刻对BEOL电性能的影响。

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