At-speed testing of deep-submicron or nano-scale integrated circuits (IC) consumes excessive power and creates hotspots and temperature gradient in the chip-under-test. The problem worsens for 3D ICs, where heat dissipation across layers is more unbalanced. These hotspots in a circuit often cause severe degradation of performance and reliability, as a rise in temperature can introduce an extra delay along paths. An effective scan architecture and test application scheme are presented to handle the problem.
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