Poly-connected MOSFETs can reduce chip area due to replacing some metal layer routing. Compared with conventional MOS, resistance of connecting poly (P2) is an additional factor which impacts MOS electrical performance, besides LDD and source/drain parasitic resistance. Conventional parasitic resistance extraction method requires a series of different gate length test structures. A new extraction method of parasitic resistance is demonstrated here, that is to extract the parasitic resistance from forward biased current vs. voltage characteristics of drain/bulk junction diode based on a single MOS test structure. Using this method, P2 layer deposition loading effect is successfully detected and poly space effect (PSE) of poly-connected MOSFETs can be well modelled in SPICE model. This new extraction method can also be applicable for conventional MOSFETs.
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