Using active cache to solve the bottleneck of bus in the parallel Radar signal process system

机译：使用Active Cache以解决并行雷达信号处理系统中总线的瓶颈

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Solving bottleneck of bus is becoming a challenging task in the design of parallel radar signal processing area. This paper has introduced a novel technology called active cache to solve this problem. By actively inserting the cache code into programs, the system will cache the remote data to local before using it. This approach is applied to the UTDSP benchmark suites, giving a good experiment result on an embedded signal processing system of four TigerSHARC101 DSPs.

机译：解决总线的瓶颈正在并行雷达信号处理区域设计中成为一个具有挑战性的任务。本文介绍了一种名为Active Cache的新技术，以解决这个问题。通过主动将缓存代码插入程序，系统将在使用之前将远程数据缓存到本地。这种方法适用于UTDSP基准套件，在嵌入式信号处理系统的嵌入式信号处理系统上提供了一个良好的实验结果。

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《International Conference on Signal Processing》|2006年||共4页
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Qin Fei; Wang Zheng; Long Teng;
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中图分类 TN911.7-53;
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4. Using active cache to solve the bottleneck of bus in the parallel Radar signal process system [C] . Qin Fei, Wang Zheng, Long Teng International Conference on Signal Processing . 2006

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5. The effects of cache coherence on the performance of parallel PDE algorithms in multiprocessor systems. [D] . Johnson, Sandra Kay. 1988

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6. Design of an FMCW radar baseband signal processing system for automotive application [O] . Jau-Jr Lin, Yuan-Ping Li, Wei-Chiang Hsu, -1

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7. Real-time parallel implementation of Pulse-Doppler radar signal processing chain on a massively parallel machine based on multi-core DSP and Serial RapidIO interconnect [O] . 2014

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Using active cache to solve the bottleneck of bus in the parallel Radar signal process system

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