In order to investigate the performance potential of3-dimensionally integrated circuits for high performance computersystems a comparative study of the interconnect structure of aRISC-processor/cache system conducted. The impact of electricalparameters of interconnection lines as well as associated packageparasitics on second level cache read access is investigated for3-dimensionally integrated circuit structures and compared toconventional PCBand advanced MCM-realizations of the system. Wiringdimensions and line drivers are optimized for the different packagingtechnologies and optimal realizations are compared with respect to cacheaccess time and power dissipation. Case studies show reductions ofeffective switching capacitances of more than an order of magnitude andreductions of second level cache access time of over 40% for optimized3D-systems compared to conventional PCB-realizations
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