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首页> 外文会议>International Symposium for Testing and Failure Analysis >Comparison of Failure for HBM ESD Testers meeting ANSI/ESD S-5.1 or the New ESDA Standard Test Method and JEDEC Standard
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Comparison of Failure for HBM ESD Testers meeting ANSI/ESD S-5.1 or the New ESDA Standard Test Method and JEDEC Standard

机译：HBM ESD测试仪失败的比较符合ANSI / ESD S-5.1或新型ESDA标准测试方法和JEDEC标准

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The ESD Association standard ANSI/ESDA S-5.1 1993 for testing sensitivity to the Human Body Model (HBM) forms the basis around which the majority of automated HBM ESD simulators have been constructed. As device pin counts increase it is unlikely that new larger simulators for > 512 pins will be capable of meeting this standard, since increased parasitics will increase the effective socket (stray) capacitance. However, such larger HBM simulators are expected to meet both the JEDEC Standard JESD-22-114A, 1997 and the newly issued ESDA Standard Test Method, ESD STM 5.1, 1998. This paper begins to evaluate the several questions regarding the correlation of HBM Withstand Voltage when used to characterize state-of-the-art semiconductor IC's, between simulators meeting the (NEW) standards JESD 22, ESD STM-5.1 and those existing simulators presently in daily use, which typically meet the (OLD) ESDA S-5.1. This paper for the first time investigates the impact of "effective" socket capacitance in the same tester; i.e., with the same discharge model and the same pin selection mechanism. The experimental investigation was based on stressing three different sub-micron CMOS technology products; firstly on a simulator meeting the OLD standard and then on a modified version of this simulator meeting the NEW standards. Electrical properties of damaged pins and physical analysis was used to establish common Failure Signatures for the two mother boards.
机译：用于测试对人体模型（HBM）的敏感性的ESD关联标准ANSI / ESDA S-5.1形成了大多数自动化HBM ESD模拟器的基础。由于设备引脚数增加，新的更大的较大模拟器> 512销的较大的模拟器将能够满足该标准，因为增加的寄生剂将增加有效的插座（杂散）电容。然而，预计这种较大的HBM模拟器将符合JEDEC标准JESD-22-114A，1997和新发布的ESDA标准测试方法，ESD STM 5.1,1998。本文开始评估有关HBM承受的几个问题用于在日常使用中满足（新）标准JESD 22，ESD STM-5.1和这些现有模拟器的模拟器之间的用于表征最先进的半导体IC的电压，通常符合（旧）ESDA S-5.1 。本文首次调查了同一测试仪中的“有效”插座电容的影响;即，具有相同的放电模型和相同的引脚选择机制。实验研究基于强调三种不同的亚微米CMOS技术产品;首先，在符合旧标准的模拟器上，然后在此模拟器的修改版本上满足新标准。损坏引脚和物理分析的电气性能用于建立两个母板的常见故障签名。

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