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A SEU-resistant, FPGA-based implementation of the substitution transformation in AES for security on satellites

机译:基于SEU的FPGA,基于FPGA的AES替代转换,在卫星上的安全性

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Designing single event upset (SEU)-resistant security for communications in satellites is an important yet challenging problem. For example, although SRAM-based FPGAs are beneficial for satellite applications, they are susceptible to SEUs. Harsh environments such as space where cosmic radiation is present increase the likelihood of these errors known as SEUs. However these errors are also expected to be prevalent in non-space applications of future nanometer technologies. Thus this is an important problem to be studied for future secure embedded systems. Satellites require an encryption mechanism for many purposes; for example, to provide secure communications with the ground station. A SEU detection technique for a symmetric encryption algorithm, such as the NIST standardized Advanced Encryption Standard (AES), is additionally challenging due to its complex non-linear task in the algorithm, namely the substitution transformation (sub_byte). This research presents an efficient solution for single-bit SEU detection in the substitution task of AES. This approach uses fewer memory cells, provides 100% single-bit SEU coverage and achieves a low failure in time (FIT). This research is important for secure communications in an error-prone harsh environment such as satellites where low cost and high reliability are important.
机译:设计单一事件令人不安(SEU) - 卫星通信的攻击安全性是一个重要而挑战性的问题。例如,虽然基于SRAM的FPGA对卫星应用有益,但它们易于SEU。诸如宇宙辐射存在的空间之类的恶劣环境增加了这些错误称为SEA的可能性。然而,这些误差也在未来纳米技术的非空间应用中普遍存在。因此,这是未来安全嵌入式系统研究的重要问题。卫星需要加密机制进行许多目的;例如,为了提供与地面站的安全通信。对对称加密算法的SEU检测技术,例如NIST标准化的高级加密标准(AES),由于其在算法中的复杂非线性任务,即替代变换(Sub_Byte),其另外挑战。本研究介绍了AES替换任务中的单位SEU检测的有效解决方案。该方法使用更少的存储器单元格,提供100%单位SEU覆盖并达到低故障(适合)。这项研究对于在低成本和高可靠性很重要的卫星处于易于易置的苛刻环境中的安全通信非常重要。

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