A 10 Gbps Analog Adaptive Equalizer and Pulse Shaping Circuit for Backplane Interface

机译：用于背板接口的10 Gbps模拟自适应均衡器和脉冲整形电路

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The speed of serial interface through a backplane channel suffers severe ISI (Inter Symbol Interference) caused by the limited bandwidth of the channel. In order to overcome the bandwidth limit, a pulse shaping circuit or an adaptive equalizer is used. This paper presents the comparison between two approaches. Prototype chip is designed for 10 Gbps serial data communication through a 34-inch transmission line with a 0.18-μ^sCMOS process. The simulation and layout results show that the adaptive equalization has superior performance in power consumption, silicon area and the jitter performance.

机译：通过背板通道的串行接口的速度会受到由信道的有限带宽引起的ISI（符号干扰的帧间）。为了克服带宽限制，使用脉冲整形电路或自适应均衡器。本文呈现了两种方法之间的比较。原型芯片设计为10 Gbps串行数据通信，通过34英寸传输线，具有0.18-μ^ SCMOS过程。模拟和布局结果表明，自适应均衡在功耗，硅面积和抖动性能方面具有卓越的性能。

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《WSEAS International Conference on Circuits, Systems, Electronics, Control and Signal Processing》|2007年||共5页
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KWISUNG YOO GUNHEE HAN; SUNGMIN PARK;
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中图分类 TN4-53;
关键词
Adaptive equalizer; Backplane; ISI; Pulse shaping; Serial interface;

机译：自适应均衡器;背板;ISI;脉冲整形;串行接口;

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专利

1. Design of a 10Gbps Analog Adaptive Equalizer and a Pre-Emphasis Filter for 34-inch Backplane Channel [J] . KWISUNG YOO, DONGMYUNG LEE, GUNHEE HAN, WSEAS Transactions on Circuits and Systems . 2006,第12期

机译：用于34英寸背板通道的10Gbps模拟自适应均衡器和预加重滤波器的设计
2. Design of a 6.25 Gbps backplane SerDes with adaptive decision feedback equalization [J] . Zhou Mingzhu, Zhu En, Wang Zhigong 高技术通讯（英文版） . 2009,第004期

机译：具有自适应决策反馈均衡的6.25 Gbps背板SerDes的设计
3. Design of a 6.25 Gbps backplane SerDes with adaptive decision feedback equalization [J] . 周明珠, Zhu En, Wang Zhigong 高技术通讯：英文版 . 2009,第004期

机译：具有自适应决策反馈均衡的6.25 Gbps背板SerDes的设计
4. A 10 Gbps Analog Adaptive Equalizer and Pulse Shaping Circuit for Backplane Interface [C] . KWISUNG YOO GUNHEE HAN, SUNGMIN PARK WSEAS International Conference on Circuits, Systems, Electronics, Control and Signal Processing . 2007

机译：用于背板接口的10 Gbps模拟自适应均衡器和脉冲整形电路
5. 10+Gbps serial data transmission over a Tyco 34" FR4 backplane channel using amplitude-optimized bit-edge equalization with an adjustment of LMS error derivation points. [D] . Zhang, Lei. 2010

机译：通过幅度优化的位边缘均衡和LMS误差导出点的调整，通过Tyco 34“ FR4背板通道进行10 + Gbps串行数据传输。
6. Dynamic feedback circuits function as a switch for shaping a maturation-inducing steroid pulse in Drosophila [O] . Morten E. Moeller, E. Thomas Danielsen, Rachel Herder, -1

机译：动态反馈电路用作在果蝇中塑造诱导成熟的类固醇脉冲的开关
7. 10+Gbps serial data transmission over a Tyco 34" FR4 backplane channel using amplitude-optimized bit-edge equalization with an adjustment of LMS error derivation points [O] . Lei Zhang -1

机译：10 + GBPS串行数据通过Tyco 34“FR4背板通道使用幅度优化的位边缘均衡，调整LMS错误导出点

A 10 Gbps Analog Adaptive Equalizer and Pulse Shaping Circuit for Backplane Interface

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