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首页> 外文会议>IMAPS and SEMI Topical Workshop on Wire Bonding >Bond Wire Yield Rate Optimization on SiP in a 3D Design Environment
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Bond Wire Yield Rate Optimization on SiP in a 3D Design Environment

机译：3D设计环境中SIP的键合线屈服率优化

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摘要

IC packaging layout has traditionally been done using conventional 2-D layout software. While 2D design tools are sufficient for single die top-down 2D type packages such as lead-frames and simple BGAs, traditional design rule checks (DRC) included in 2D layout tools are not able to confirm or simulate efficient wire bonding assembly of advanced System-in-Package (SiP) designs such as Stacked Die, stacked and folded packages, and densely wired I.C.s with multiple power rings and multiple bond shells. The package designer currently completes the design in 2D, not knowing if the 3D package he designed is truly manufacturable or not. The manufacturing engineer is thus forced to perform a long series of trial-and-error prototype wire bonding runs, which take substantial time. The package may be mass-produced with resultant low yields, contributing to higher costs and further increasing time-to-market, and can ultimately require a complete redesign after much wasted time and resources. Dramatically improved reliability and yield, and decreased time-to-market for stacked die packages, densely wire bonded I.C.s and other 3D package types is possible with a 3D design and collaboration process which integrates the design, optimization, verification, manufacturing and inspection processes into a globally accessible seamless system. A 3D design and collaboration system provides data access to all related departments to optimize the design for maximum performance, highest yield and fastest time-to-market. The package designers can input 3D wire bond assembly parameters during the design process. The design is modeled in 3D, and the assembly parameters are simulated, verified, and optimized for maximum yield during the design process. When the resultant optimized design arrives in production, the trial-and-error prone setup process can be dramatically reduced, and the resultant Yield Rate can be vastly improved.
机译：传统上，IC包装布局使用传统的2-D布局软件进行。虽然2D设计工具足以用于单芯片上下2D型封装，如引导帧和简单的BGA，但在2D布局工具中包含的传统设计规则检查（DRC）无法确认或模拟高级系统的高效电线键合组件-in-Packice（SIP）（SIP）设计，如堆叠模具，堆叠和折叠的封装，以及具有多个电源环和多个键壳的密集有线IC。包装设计人员目前在2D中完成设计，不知道他设计的3D包是否真正的制造。因此，制造工程师被迫执行长一系列的试验和误差原型引线键合运行，这需要大量的时间。该包装可以用结果低产率大规模生产，有助于更高的成本和进一步提高上市时间，并最终需要在浪费时间和资源浪费的时间和资源之后完全重新设计。大大提高了可靠性和收益率，并降低了堆叠模具封装的上市时间，密集导线键合的IC和其他3D封装类型可以使用3D设计和协作过程，这集成了设计，优化，验证，制造和检查过程中的设计，优化，验证，制造和检查过程全球可访问的无缝系统。 3D设计和协作系统提供对所有相关部门的数据访问，以优化设计最大性能，最高产量和最快的上市时间。包装设计人员可以在设计过程中输入3D线键组件参数。该设计以3D建模，并在设计过程中模拟，验证和优化组装参数，优化并优化。当所产生的优化设计到达生产时，可以显着降低试验和错误的安装过程，并且可以大大提高所得到的屈服率。

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