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首页> 外文会议>SPIE conference on Southeast Asian International Advances in Micro/Nanotechnology >Schematic-Based 4/16/64 Order Quadrature Amplitude Modulation Mapper-Demapper Implementation for 256 Sub Channels Orthogonal Frequency Division Multiplexing Model on FPGA Xilinx SPARTAN 3E
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Schematic-Based 4/16/64 Order Quadrature Amplitude Modulation Mapper-Demapper Implementation for 256 Sub Channels Orthogonal Frequency Division Multiplexing Model on FPGA Xilinx SPARTAN 3E

机译：基于示意性的4/16/64阶数正交幅度调制MAPPER-DEMAPPER在FPGA Xilinx Spartan 3E上进行256个子通道正交频分复用模型

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摘要

Orthogonal Frequency Division Multiplexing (OFDM) is a modulation technique which provides higher bit rate and efficient bandwidth. This paper presents an implementation of a 4/16/64 Order Quadrature Amplitude Modulation (QAM) Mapper-Demapper for 256 Sub channel OFDM Model on Xilinx SPARTAN 3E Field-Programmable Gate Array (FPGA) series, using schematic approach. This QAM-OFDM model is reconfigurable in term of its QAM order. The result shows that under the clock frequency around 262 MHz, the implementation works well, high precision is achieved at its serial output. A precision process conducted at 20 ns internal clock input period, with the 25 Mbps input bit rate requires 81.94 μs QAM processing-time. The implementation consumes about 80 % of the total FPGA slices (3736 slices).
机译：正交频分复用（OFDM）是一种提供更高比特率和高效带宽的调制技术。本文介绍了Xilinx Spartan 3E现场可编程门阵列（FPGA）系列上的256个副通道OFDM模型的4/16/64级正交幅度调制（QAM）映射器-Demapper的实施。此QAM-OFDM模型可在其QAM顺序的任期内重新配置。结果表明，在262 MHz的时钟频率下，实施方式很好，在其串行输出处实现了高精度。在20NS内部时钟输入时段进行的精度过程，具有25 Mbps输入比特率需要81.94μsQAM处理时间。该实施消耗了总FPGA片的80％（3736切片）。

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