首页> 外文会议>Southeast Asian international advances in microanotechnology >Schematic-Based 4/16/64 Order Quadrature Amplitude Modulation Mapper-Demapper Implementation for 256 Sub Channels Orthogonal Frequency Division Multiplexing Model on FPGA Xilinx SPARTAN 3E
【24h】

Schematic-Based 4/16/64 Order Quadrature Amplitude Modulation Mapper-Demapper Implementation for 256 Sub Channels Orthogonal Frequency Division Multiplexing Model on FPGA Xilinx SPARTAN 3E

机译:在FPGA Xilinx SPARTAN 3E上基于原理图的4/16/64阶正交幅度调制映射器-映射器实现256个子通道正交频分复用模型

获取原文
获取原文并翻译 | 示例

摘要

Orthogonal Frequency Division Multiplexing (OFDM) is a modulation technique which provides higher bit rate and efficient bandwidth. This paper presents an implementation of a 4/16/64 Order Quadrature Amplitude Modulation (QAM) Mapper-Demapper for 256 Sub channel OFDM Model on Xilinx SPARTAN 3E Field-Programmable Gate Array (FPGA) series, using schematic approach. This QAM-OFDM model is reconfigurable in term of its QAM order. The result shows that under the clock frequency around 262 MHz, the implementation works well, high precision is achieved at its serial output. A precision process conducted at 20 ns internal clock input period, with the 25 Mbps input bit rate requires 81.94 us QAM processing-time. The implementation consumes about 80 % of the total FPGA slices (3736 slices).
机译:正交频分复用(OFDM)是一种调制技术,可提供更高的比特率和有效的带宽。本文采用示意性方法,介绍了在Xilinx SPARTAN 3E现场可编程门阵列(FPGA)系列上实现256子信道OFDM模型的4/16/64阶正交幅度调制(QAM)映射器-Demapper的实现。此QAM-OFDM模型可以根据其QAM顺序进行重新配置。结果表明,在大约262 MHz的时钟频率下,该实现效果很好,其串行输出实现了高精度。在20 ns内部时钟输入周期,25 Mbps输入比特率下进行的精密处理需要81.94 us QAM处理时间。该实现消耗了大约FPGA片(3736片)总数的80%。

著录项

相似文献

  • 外文文献
  • 专利
获取原文

客服邮箱:kefu@zhangqiaokeyan.com

京公网安备:11010802029741号 ICP备案号:京ICP备15016152号-6 六维联合信息科技 (北京) 有限公司©版权所有
  • 客服微信

  • 服务号