Research and Design for 2D-FFT Processor Based on FPGA

机译：基于FPGA的2D-FFT处理器研究与设计

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摘要

In this paper, a 2D-FFT processor design on CORDIC algorithm has proposed. This design extracts the radix-4 algorithm in FFT as the foundation, uses the assembly line technology to enhance the turnover rate for the whole system, and has many characteristics with the simple hardware architecture, low component, stable running and high precision. This design has carried on the timing simulation on Altera chip EP2C35F672C6, can satisfy 50 MHz system clock.

机译：本文提出了关于CORDIC算法的2D-FFT处理器设计。这种设计提取了FFT中的基数-4算法作为基础，采用装配线技术提高整个系统的周转率，并具有简单的硬件架构，低元件，稳定运行和高精度的特点。该设计在Altera芯片EP2C35F672C6上进行了定时仿真，可以满足50 MHz系统时钟。

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《International Conference on Innovation Manufacturing and Engineering Management》|2013年||共5页
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作者
Xiaoyu Cheng; Jun Yang; Yunhua Zuo;
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原文格式 PDF
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中图分类 TH16-53;
关键词
2D-FFT Processor; FPGA; CORDIC Algorithm;

机译：2D-FFT处理器;FPGA;CORDIC算法;

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3. Accelerate system performance with hybrid multiprocessing & FPGAs: Multiprocessing is becoming a key differentiator for FPGA-based processor architectures [J] . DAN ISAACS, BRUCE KARSTEN, ED TREXEL Embedded Systems Europe . 2007,第86期

机译：借助混合多处理和FPGA来提高系统性能：多处理正成为基于FPGA的处理器架构的关键差异化因素
4. Research and Design for 2D-FFT Processor Based on FPGA [C] . Xiaoyu Cheng, Jun Yang, Yunhua Zuo International Conference on Innovation Manufacturing and Engineering Management . 2013

机译：基于FPGA的2D-FFT处理器研究与设计
5. FPGA design of a CDMA system for multiuser detection based on iterative processing. [D] . Dodd, Russell. 2009

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7. Figure 9: Block diagram of the proposed processor compared with the traditional 2D-FFT processor. [O] . -1

机译：图9：与传统的2D-FFT处理器相比，所提出的处理器的框图。

Research and Design for 2D-FFT Processor Based on FPGA

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