Design of Broadband, High-Speed Dual-Modulus Prescaler for Multi-Mode PLL Frequency Synthesizer

机译：多模PLL频率合成器宽带，高速双模压梯设计的设计

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A architecture of multi-mode PLL frequency synthesizer one can meet a variety of communication standards is presented in this paper, which can provide each mode with the required frequency, while reducing the system's hardware cost. Optimized broadband high-speed dual-mode prescaler (DMP)'s internal structure, the principle of circuit design and its layout is introduced. The DMP is produced by 0.18μm CMOS technology. The post simulation results show that with the 1.8V power, the DMP's operating frequency range is 0.4 ～ 9.6GHz, the power consumption is 7.6mA.

机译：本文提出了一种多模PLL频率合成器的架构，可以满足各种通信标准，可以提供所需频率的每种模式，同时降低系统的硬件成本。优化宽带高速双模预分频器（DMP）的内部结构，电路设计原理及其布局。 DMP由0.18μmCMOS技术产生。后仿真结果表明，随着1.8V的功率，DMP的工作频率范围为0.4〜9.6GHz，功耗为7.6mA。

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《International Conference on Mechanical Automation and Materials Engineering》|2013年||共5页
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作者
Jiang Xuefei; Fan Xiangning;
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中图分类 TB3-53;
关键词
Multi-mode PLL frequency synthesizer; Dual-modulus prescaler; Broadband; High-speed;

机译：多模PLL频率合成器;双模预分频器;宽带;高速;

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1. A 1.8 Ghz-2.4 Ghz Fully Programmable Frequency Divider And A Dual-Modulus Prescaler For High Speed Frequency Operation In PLL System Using 250nm Cmos Technology [J] . Harsh joshi, Prof.Sanjeev M.Ranjan International Journal of Engineering Research and Applications . 2012,第4期

机译：使用250nm Cmos技术在PLL系统中实现1.8 Ghz-2.4 Ghz完全可编程分频器和双模预分频器，以在PLL系统中实现高速频率工作
2. Low Voltage and High Speed Dual-Modulus Prescaler with E-TSPC Technology for Frequency Synthesizer [J] . Xiang Hongyong, Wang Chunhua, Guo Xiaorong, National Academy Science Letters . 2015,第3期

机译：采用E-TSPC技术的低压高速双模预分频器，用于频率合成器
3. High-speed architecture for a programmable frequency divider and a dual-modulus prescaler [J] . Larsson P. IEEE Journal of Solid-State Circuits . 1996,第5期

机译：可编程分频器和双模预分频器的高速架构
4. Design of Broadband, High-Speed Dual-Modulus Prescaler for Multi-Mode PLL Frequency Synthesizer [C] . Jiang Xuefei, Fan Xiangning International Conference on Mechanical Automation and Materials Engineering . 2013

机译：多模PLL频率合成器宽带，高速双模压梯设计的设计
5. Design and optimization of low power PLL frequency synthesizer [D] . Chen, Wu-Hsin 2011

机译：低功耗PLL频率合成器的设计与优化
6. A broadband chip-scale optical frequency synthesizer at 2.7 × 10−16 relative uncertainty [O] . Shu-Wei Huang, Jinghui Yang, Mingbin Yu, 2016

机译：相对不确定度为2.7×10-16的宽带芯片级光频率合成器
7. CMOS dual-modulus prescaler design for RF frequency synthesizer applications. [O] . 2005

机译：CmOs双模预分频器设计，适用于RF频率合成器应用。

Design of Broadband, High-Speed Dual-Modulus Prescaler for Multi-Mode PLL Frequency Synthesizer

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