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FPGA implementation of conventional and vedic algorithm for energy efficient multiplier

机译：用于节能乘法器的传统和Vedic算法的FPGA实现

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Digital Signal Processor (DSP) as well as other microcontroller applications requires fast and low power consumption systems to compete with the advanced technology. The performance of the DSP applications mainly depends on the multiplier, because the multiplication requires more iterations, long time and large area of the system than other computations. Hence to improve the performance of the system it is required to have high speed and low power consumption multiplier. In this paper we proposed the comparative study of two different algorithms, first one is the conventional method called as ???Booth Multiplier??? and other is the vedic method ???Nikhilam Navatascaram Dasatah??? using reversible logic gates. Both the multipliers are designed and implemented by using Xilinx 13.2 ISE simulator. Comparative results of both the multipliers are analyzed in terms of delay, area and power consumption.
机译：数字信号处理器（DSP）以及其他微控制器应用需要快速和低功耗系统，以与先进的技术竞争。 DSP应用程序的性能主要取决于乘法器，因为乘法需要更多的迭代，长时间和大面积的系统而不是其他计算。因此，为了提高系统的性能，需要具有高速和低功耗倍增器。在本文中，我们提出了两种不同算法的比较研究，首先是传统方法称为???展位倍增器???和其他是vedic方法??? nikhilam navatascaram dasatah ???使用可逆逻辑门。乘数都是通过使用Xilinx 13.2 ISE模拟器设计和实现的。在延迟，区域和功耗方面分析了乘法器的比较结果。

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