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Multi-mode Low-latency Software-defined Error Correction for Data Centers

机译：数据中心的多模式低延迟软件定义的纠错

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Flash memories are gaining prominence for utilizing in large scale data centers (DCs) due to their high memory density, low power consumption and heat dissipation, and high access speed characteristics. The rate of degradation for a flash memory is largely affected by the amount and frequency of the erase/write operations, which is a challenge in the DC context that serves dynamically changing workloads. Adaptive Error Correction Code (AECC) schemes have been introduced for changing the error correction algorithm based on the reliability state of the flash. In this study we show that hard decision (bit-flipping) and soft-decision decoding (Belief Propagation) class of algorithms for Low Density Parity Check (LDPC) decoders complement each other for utilizing in the flash based DCs in order to meet the dynamically changing reliability level. We propose a new family of ECC to improve the reliability of flash memory. Our Monte-Carlo simulations and Field Programmable Gate Array (FPGA) based hardware implementation analysis show that LDPC decoders are suitable for balancing the throughput, decoding performance and reliability requirements in DCs.
机译：闪存由于其高存储器密度，低功耗和散热而利用大规模数据中心（DCS）而获得突出，并且高功耗和高接近速度特性。闪存的劣化率很大程度上受到擦除/写入操作的量和频率的影响，这是一种用于动态变化工作负载的DC上下文中的挑战。已经引入了自适应纠错码（AECC）方案以改变基于闪光的可靠性状态的纠错算法。在这项研究中，我们表明，用于低密度奇偶校验检查（LDPC）解码器的硬判决（比特翻转）和软判决解码（信仰传播）类别的算法，用于利用基于闪存的DC，以便以动态地满足速度改变可靠性水平。我们提出了一个新的ECC系列，提高闪存的可靠性。我们的Monte-Carlo仿真和现场可编程门阵列（FPGA）的硬件实现分析表明，LDPC解码器适用于平衡DCS中的吞吐量，解码性能和可靠性要求。

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