Based on the objective of keeping the MOS technology evolution, alternative technologies have been studied and some of them have presented quite interesting results, such as the Silicon-on-Insulator (SOI) one. Characterized by the presence of an insulator layer between the silicon substrate and the transistor active region, SOI devices were initially used mainly in harsh environments, in which low sensitivity to temperature variation (1,2) and high hardness against transient radiation effects are required (3), and have been increasingly used during the last decade for general purpose applications. In spite of the SOI transistors longer life duration, the issue of the charges control in the channel region is still considered a problem for shorter devices. In order to keep the continuous decrease in the MOS transistors dimensions, the academic community is studying the applicability of a multiple gate structure. The multiple gate architecture has presented a better behavior when compared to the single gate one (4,5). Among many observed advantages, it is possible to mention an increase in the transconductance, a better short channel effect and an almost ideal subthreshold slope.
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